Patents by Inventor Wen-Cheng CHIU

Wen-Cheng CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250022809
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, then a cladding layer is formed to cover the electronic element, and a shielding layer is formed on the cladding layer to cover the electronic element. The cladding layer is bonded to a shielding structure, and the shielding structure is located between the shielding layer and the electronic element, so as to prevent the electronic element from being subjected to external electromagnetic interference via multiple shielding mechanisms of the shielding structure and the shielding layer.
    Type: Application
    Filed: October 12, 2023
    Publication date: January 16, 2025
    Inventors: Wen-Jung TSAI, Chih-Hsien CHIU, Chien-Cheng LIN, Shao-Tzu TANG, Ko-Wei CHANG
  • Patent number: 10702494
    Abstract: The present invention is related to a method for cancer treatment comprising a step of administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical composition comprising ferrous amino acid chelate and a pharmaceutically acceptable carrier. By means of amino acid chelating to ferrous and maintaining chelating state through the stomach, the pharmaceutical composition in accordance with the present invention would not cause any weight variation, and is suitable for inhibiting or treating cancer.
    Type: Grant
    Filed: September 3, 2014
    Date of Patent: July 7, 2020
    Assignee: Profeat Biotechnology Co., Ltd.
    Inventors: Tsun-Yuan Lin, Mu-Kuei Chen, Tsang-Tse Chen, Chai-Hui Fu, Hsun-Jin Jan, Wen-Cheng Chiu
  • Patent number: 9041129
    Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: May 26, 2015
    Assignee: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Chia-Hua Ho, Ming-Daou Lee, Wen-Cheng Chiu, Cho-Lun Hsu
  • Publication number: 20150065569
    Abstract: The present invention is related to a method for cancer treatment comprising a step of administering to a subject in need thereof a therapeutically effective amount of a pharmaceutical composition comprising ferrous amino acid chelate and a pharmaceutically acceptable carrier. By means of amino acid chelating to ferrous and maintaining chelating state through the stomach, the pharmaceutical composition in accordance with the present invention would not cause any weight variation, and is suitable for inhibiting or treating cancer.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 5, 2015
    Inventors: Tsun-Yuan Lin, Mu-Kuei Chen, Tsang-Tse Chen, Chai-Hui Fu, Hsun-Jin Jan, Wen-Cheng Chiu
  • Patent number: 8835894
    Abstract: The present invention discloses a resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 16, 2014
    Assignee: National Applied Research Laboratories
    Inventors: Ming-Daou Lee, ChiaHua Ho, Cho-Lun Hsu, Wen-Cheng Chiu
  • Publication number: 20140077150
    Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.
    Type: Application
    Filed: November 22, 2013
    Publication date: March 20, 2014
    Applicant: National Applied Research Laboratories
    Inventors: CHIA-HUA HO, MING-DAOU LEE, WEN-CHENG CHIU, CHO-LUN HSU
  • Publication number: 20130221313
    Abstract: The present invention discloses an ultra high density resistive memory structure and a method for fabricating the same. The memory structure comprises a plurality of memory cells. Each memory cell further comprises two separate upper sub-electrodes fabricated from an upper electrode, two separate lower sub-electrodes fabricated from a lower electrode and intersecting the upper sub-electrodes, and a resistive layer arranged between the upper sub-electrodes and the lower sub-electrodes. Thereby, four sub-memory cells are formed in the intersections of the two upper sub-electrodes, the two lower sub-electrodes, and the resistive layer. Thus is increased the density of a memory structure in an identical area.
    Type: Application
    Filed: April 20, 2012
    Publication date: August 29, 2013
    Inventors: Ming-Daou LEE, ChiaHua HO, Cho-Lun HSU, Wen-Cheng CHIU