Patents by Inventor Wen-Cheng Tien

Wen-Cheng Tien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9006809
    Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: April 14, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Fei Xie, Wen Cheng Tien, Ya Ping Chen, Li Bin Man, Kuo Jung Chen, Yu Liu, Tian Yi Zhang, Sisi Xie
  • Publication number: 20140252457
    Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Fei XIE, Wen Cheng TIEN, Ya Ping CHEN, Li Bin MAN, Kuo Jung CHEN, Yu LIU, Tian Yi ZHANG, Sisi XIE
  • Patent number: 8765592
    Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Fei Xie, Wen Cheng Tien, Ya Ping Chen, Li Bin Man, Kuo Jung Chen, Yu Liu, Tian Yi Zhang, Sisi Xie
  • Publication number: 20130256787
    Abstract: A method for contacting MOS devices. First openings in a photosensitive material are formed over a substrate having a top dielectric in a first die area and a second opening over a gate stack in a second die area having the top dielectric, a hard mask, and a gate electrode. The top dielectric layer is etched to form a semiconductor contact while etching at least a portion the hard mask layer thickness over a gate contact area exposed by the second opening. An inter-layer dielectric (ILD) is deposited. A photosensitive material is patterned to generate a third opening in the photosensitive material over the semiconductor contact and a fourth opening inside the gate contact area. The ILD is etched through to reopen the semiconductor contact while etching through the ILD and residual hard mask if present to provide a gate contact to the gate electrode.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: FEI XIE, WEN CHENG TIEN, YA PING CHEN, LI BIN MAN, KUO JUNG CHEN, YU LIU, TIAN YI ZHANG, SISI XIE
  • Patent number: 5837426
    Abstract: A photolithographic process which provides reduced line widths or reduced inter-element line spaces for the circuit elements on an IC chip, allowing the IC chip to have a higher degree of integration. The photolithographic process includes a double-exposure process on the same wafer defined by placing either the same photomask at two different positions or by using two photomasks. In the first exposure process, a first selected set of areas on the photoresist layer is exposed through the photomask. In the second exposure process, the photomask is shifted to predetermined positions interleaving or overlapping the positions where the first selected set of exposed areas are formed, or alternatively a second photomask replaces the first photomask. The second photomask has a plurality of patterns arranged in positions correspondingly interleaving or overlapping the positions where the first selected set of exposed areas is formed.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: November 17, 1998
    Assignee: United Microelectronics Corp.
    Inventors: Che-Pin Tseng, Wei-Jiang Lin, Wen-Cheng Tien, Yun-Kuei Yang