Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. In addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. The method includes forming a backside conductive contact in the contact opening.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming an isolation structure surrounding a lower portion of the fin structure, forming a protection layer over the isolation structure, etching the fin structure, the protection layer and the isolation structure to form a first recess in the fin structure and a second recess in the isolation structure, forming a source/drain feature to fill the first recess, and forming an interlayer dielectric layer over the source/drain feature and filling the second recess.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate and a nanostructure stack. The method includes forming an isolation layer over the base and surrounding the fin. The method includes forming a first protection layer over the nanostructure stack and the isolation layer. The method includes forming a second protection layer over the first protection layer. The method includes forming a mask layer over the second protection layer. The top portion of the second protection layer protrudes from the mask layer. The method includes thinning the top portion of the second protection layer. The method includes removing the mask layer. The method includes removing the first protection layer and the second protection layer over the nanostructure stack. The method includes forming a gate stack wrapped around the nanostructure stack.

Abstract: A semiconductor device, a semiconductor chip and manufacturing methods thereof are provided. The semiconductor device includes: channel structures, vertically spaced apart from one another; a gate structure, intersecting the channel structures and wrapping around each of the channel structures; source/drain structures, in lateral contact with the channel structures from opposite sides of the channel structures; and protection structures, separately disposed along a bottom surface of the gate structure, wherein the channel structures are located between the protection structures, and the protection structures comprise a semiconductor material.

Abstract: The present disclosure provides a semiconductor structure with having a source/drain feature with a central cavity, and a source/drain contact feature formed in central cavity of the source/drain region, wherein the source/drain contact feature is nearly wrapped around by the source/drain region. The source/drain contact feature may extend to a lower most of a plurality semiconductor layers.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a first contact structure formed over a first side of the first S/D structure, and a portion of the first contact structure is lower than a top surface of the first S/D structure. The semiconductor structure includes a second contact structure formed over a second side of the first S/D structure, and the second contact structure is in direct contact with the first contact structure.

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.

Abstract: A multifunctional oxide based negative capacitance thin film transistor (NC-TFT) is built on glass or on flexible substrates, instead of on the single crystal substrates. It is therefore suitable for low-cost and large-area electronics, transparent electronics, or flexible electronics applications. The NC-TFT includes a semiconductor Magnesium Zinc Oxide (MZO) as the channel layer and a Nickel doped MZO ferroelectric material (NMZO) as the gate dielectric layer. Also disclosed are articles of manufacture methods of building the NC-TFT on glass and its transparent version NC-TTFT on glass.

Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.

Abstract: Embodiments are directed to a flexible high voltage thin film transistor (f-HVTFT) with a center-symmetric circular configuration. The f-HVTFT includes a ring-shaped oxide semiconductor channel, a ring-shaped gate, a ring-shaped source, and a circular drain. The source and gate each have multiple connections to respective electrode pads, enabling stable and identical electrical characteristics and blocking voltage while the f-HVTFT is subject to bending from random directions. The f-HVTFT enables a high blocking voltage over 100 V, on-current over 100 ?A, and low off-current of 0.1 pA, which makes it suitable for power management of self-powered wearable electronic systems.

Abstract: Embodiments are directed to a flexible high voltage thin film transistor (f-HVTFT) with a center-symmetric circular configuration. The f-HVTFT includes a ring-shaped oxide semiconductor channel, a ring-shaped gate, a ring-shaped source, and a circular drain. The source and gate each have multiple connections to respective electrode pads, enabling stable and identical electrical characteristics and blocking voltage while the f-HVTFT is subject to bending from random directions. The f-HVTFT enables a high blocking voltage over 100 V, on-current over 100 ?A, and low off-current of 0.1 pA, which makes it suitable for power management of self-powered wearable electronic systems.

Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.

Abstract: Magnesium Zinc Oxide (MZO)—based high voltage thin film transistor (MZO-HVTFT) is built on a transparent substrate, such as glass. The device has the circular drain and ring-shaped source and gate to reduce non-uniformity of the electric field distribution. Controlled Mg doping in the channel and modulated Mg doping in a transition layer located at the channel-gate dielectric interface improve the device's operating stability and increase its blocking voltage capability over 600V. The MZO HVTFT can be used for fabricating the micro-inverter in photovoltaic system on glass (PV-SOG), and for self-powered smart glass.