Abstract: In one embodiment, a vectorless IVD methodology may be used to estimate IVD issues for an integrated circuit earlier in the design cycle of the integrated circuit, e.g. when corrective actions may still be taken to correct IVD failures. In the methodology, scan chains for various clusters in the integrated circuit may be identified, even though the scan chains may still be subject to change as the design evolves. A power integrity tool may analyze the scan chains based on a probability of transitions in the devices within the scan chain (e.g. flops) for a theoretical worst-case test vector. If the result of analysis identifies IVD failures in the clusters, corrective action may be taken such as modifying the design. Alternatively, the corrective action may include identifying one or more flops that experience failure as devices to be excluded from the test vector generation process for scan testing.

Abstract: In one embodiment, a vectorless IVD methodology may be used to estimate IVD issues for an integrated circuit earlier in the design cycle of the integrated circuit, e.g. when corrective actions may still be taken to correct IVD failures. In the methodology, scan chains for various clusters in the integrated circuit may be identified, even though the scan chains may still be subject to change as the design evolves. A power integrity tool may analyze the scan chains based on a probability of transitions in the devices within the scan chain (e.g. flops) for a theoretical worst-case test vector. If the result of analysis identifies IVD failures in the clusters, corrective action may be taken such as modifying the design. Alternatively, the corrective action may include identifying one or more flops that experience failure as devices to be excluded from the test vector generation process for scan testing.