Patents by Inventor Wen-Chieh Lu
Wen-Chieh Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107414Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
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Publication number: 20240073378Abstract: A projection apparatus including a light source module, an eccentric-collimating lens, a prism lens group, a light valve and a projection lens is provided. The light source module is configured to provide an illumination light beam. The eccentric-collimating lens is disposed between the light sources and the light valve on a transmission path of the illumination light beam. The light valve is configured to convert the illumination light beam into an image light beam. The projection lens is configured to project the image light beam out of the projection apparatus. A first included angle between a first transmission direction of the illumination light beam incident on the eccentric-collimating lens and a central axis of the eccentric-collimating lens is greater than 0. The first transmission direction and a second transmission direction of the image beam exiting from the light valve are perpendicular to each other.Type: ApplicationFiled: August 24, 2023Publication date: February 29, 2024Applicant: Coretronic CorporationInventors: Chun-Hsin Lu, Jen-Wei Kuo, Wen-Chieh Chung
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Publication number: 20240069425Abstract: An illumination system including two light source modules, two light guiding modules, a first reflector, and a light homogenization element is provided. The two light guiding modules are respectively disposed on transmission paths of light beams generated by the two light source modules to generate two guiding light beams. One of the guiding light beams is reflected to the light homogenization element by the first reflector. The other of the guiding light beams is directly transmitted to the light homogenization element. The guiding light beams are emitted from the light homogenization element and form an illumination light beam. A projection apparatus is also provided.Type: ApplicationFiled: August 24, 2023Publication date: February 29, 2024Applicant: Coretronic CorporationInventors: Chun-Hsin Lu, Jen-Wei Kuo, Wen-Chieh Chung
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Patent number: 10777559Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.Type: GrantFiled: March 22, 2019Date of Patent: September 15, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
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Publication number: 20200273862Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.Type: ApplicationFiled: March 22, 2019Publication date: August 27, 2020Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
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Patent number: 10672864Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 11, 2019Date of Patent: June 2, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Patent number: 10475794Abstract: A method for fabricating semiconductor device includes the steps of: forming a first bit line structure on a substrate; forming a first spacer adjacent to the first bit line structure; forming an interlayer dielectric (ILD) layer adjacent to the first spacer; removing part of the ILD layer and part of the first spacer to expose a sidewall of the first bit line structure; and forming a first storage node contact isolation structure adjacent to the first bit line structure, wherein the first storage node contact isolation structure contacts the first bit line structure and the first spacer directly.Type: GrantFiled: July 3, 2018Date of Patent: November 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Po-Han Wu, Fu-Che Lee, Chien-Cheng Tsai, Tzu-Tsen Liu, Wen-Chieh Lu
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Patent number: 10361209Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.Type: GrantFiled: July 24, 2018Date of Patent: July 23, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
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Publication number: 20190206982Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Patent number: 10276650Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 21, 2018Date of Patent: April 30, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20180350817Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.Type: ApplicationFiled: July 24, 2018Publication date: December 6, 2018Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
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Publication number: 20180308923Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: ApplicationFiled: March 21, 2018Publication date: October 25, 2018Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20180261603Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.Type: ApplicationFiled: April 5, 2017Publication date: September 13, 2018Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
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Patent number: 10074656Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.Type: GrantFiled: April 5, 2017Date of Patent: September 11, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho, Wen-Chieh Lu, Li-Wei Liu
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Publication number: 20060022572Abstract: A kind of enhanced structure for full-color fluorescent screens, which includes a kind of white-color or achromatic fluorescent powder sensible to ultraviolet rays which, when illuminating and absorbing, emits RGB lights in orange red, green and violet blue that interact and configure to form a full-color screen on a substrate, which is printed with orange red layer, green layer and violet blue layer in the size, pitch, overlapping, configuration and layout as that of the primary color. the RGB layers come in the size, pitch, overlapping, configuration and layout as that of the primary color and in the dark, color lights are emitted when illuminated by the ultraviolet ray to the fluorescent light layers and the color lights then, depending on the size, pitch and overlapping of the fluorescent powder dots, emit RGB lights in different intensities and the RGB color lights of different tones and intensities come to form a full-color figure of full color scale.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Inventor: Wen-Chieh Lu
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Publication number: 20050172986Abstract: An umbrella safety and alarm enhancement device, particularly an enhancement device installed on an umbrella to provide electro luminescence lighting or flashing at nighttime, forming a larger lighting rage, giving strong short-wave lighting alarm at night or in a rainy or foggy environment, the short waves of the electro luminescence is free from obstruction by rain or fog. The strong electro luminescence flashing light can be seen from a distance to prevent accidents and ensure pedestrians' safety.Type: ApplicationFiled: February 6, 2004Publication date: August 11, 2005Inventor: Wen-Chieh Lu