Patents by Inventor Wen-Chieh Tu

Wen-Chieh Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200312804
    Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Pai-Sheng Cheng, Wen-Chieh Tu
  • Patent number: 10777525
    Abstract: A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 15, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Pai-Sheng Cheng, Wen-Chieh Tu
  • Publication number: 20090091028
    Abstract: A semiconductor device including a semiconductor substrate, a contact pad, a passivation layer, a bump, and a seeding layer is provided. The semiconductor substrate has an active surface. The contact pad is disposed on the active surface. The passivation layer is disposed on the active surface and exposes a central part of the contact pad. The seeding layer is disposed on the exposed central part of the contact pad. The bump has a top surface, a bottom surface opposite to the top surface, and a side surface connecting the top surface and the bottom surface. The bump is disposed on the seeding layer. The bump is placed in contact with the seeding layer by the bottom surface and by part of the side surface.
    Type: Application
    Filed: April 28, 2008
    Publication date: April 9, 2009
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chiu-Shun Lin, Chia-Hui Wu, Wen-Chieh Tu
  • Publication number: 20050133912
    Abstract: An electrical connection structure for electrically connecting with a chip and a bearing element is provided. The chip has a first surface. The bearing element has a second surface corresponding to the first surface. The electrical connection structure includes two outer contact points on the first surface, M inner contact points on the first surface and correspond to the inner side of the first surface, two outer conducting wires on the second surface, and M inner conducting wires on the second surface and corresponding to the M inner contact points. The chip and the bearing element are electrically connected via the electrical contact between the two outer contact points and the two outer conducting wires, and the electrical connection between the M inner contact points and the M inner conducting wires. M is a positive integer greater than or equal to 2.
    Type: Application
    Filed: November 24, 2004
    Publication date: June 23, 2005
    Inventors: Chia-Hui Wu, Pai-Sheng Cheng, Wen-Chieh Tu