Patents by Inventor Wen-Chih Chiou

Wen-Chih Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210335694
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20210327836
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, through substrate vias, conductive pillars and dummy conductive pillars. The interconnection structure is disposed at a front side of the semiconductor substrate, and comprises a stack of dielectric layers and interconnection elements spreading in the stack of dielectric layers. The through substrate vias separately penetrate through the semiconductor substrate and the stack of dielectric layers. The conductive pillars are disposed at a front side of the interconnection structure facing away from the semiconductor substrate, and respectively in electrical connection with one of the through substrate vias. The dummy conductive pillars are disposed aside the conductive pillars at the front side of the interconnection structure.
    Type: Application
    Filed: July 1, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Publication number: 20210327866
    Abstract: A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.
    Type: Application
    Filed: July 21, 2020
    Publication date: October 21, 2021
    Inventors: Chen-Hua Yu, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 11145623
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Publication number: 20210313309
    Abstract: Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Publication number: 20210305200
    Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.
    Type: Application
    Filed: September 14, 2020
    Publication date: September 30, 2021
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20210273013
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first logic die including a first through via, an image sensor die hybrid bonded to the first logic die, and a second logic die bonded to the first logic die. A front side of the first logic die facing a front side of the image sensor die. A front side of the second logic die facing a backside of the first logic die. The second logic die comprising a first conductive pad electrically coupled to the first through via.
    Type: Application
    Filed: June 2, 2020
    Publication date: September 2, 2021
    Inventors: Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11101240
    Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu
  • Publication number: 20210257339
    Abstract: A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.
    Type: Application
    Filed: April 12, 2021
    Publication date: August 19, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 11063008
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11056419
    Abstract: A semiconductor device includes a through-substrate via extending from a frontside to a backside of a semiconductor substrate. The through-substrate via includes a concave or a convex portion adjacent to the backside of the semiconductor substrate. An isolation film is formed on the backside of the semiconductor substrate. A conductive layer includes a first portion formed on the concave or convex portion of the through substrate via and a second portion formed on the isolation film. A passivation layer partially covers the conductive layer.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Ming-Tsu Chung, HsiaoYun Lo, Hong-Ye Shih, Chia-Yin Chen, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11043481
    Abstract: A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Patent number: 11037904
    Abstract: Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating the first chip, bonding the first chip to a second chip. The first chip includes a first semiconductor substrate and a first interconnect structure on a front side of the first semiconductor substrate. The singulating the first chip includes etching through a back side of the first semiconductor substrate through the first interconnect structure.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11004832
    Abstract: A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Pin Chang, Weng-Jin Wu, Wen-Chih Chiou, Chen-Hua Yu
  • Patent number: 11004741
    Abstract: An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiung Wu, Kuan-Liang Lai, Ming-Tsu Chung, Hong-Ye Shih, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 10978424
    Abstract: A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically connected to the first integrated circuit component. The third integrated circuit component is stacked on and electrically connected to the second integrated circuit component. The dielectric encapsulation laterally encapsulates the second integrated circuit component or the third integrated circuit component. In addition, manufacturing methods of the above-mentioned semiconductor device are provided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou
  • Patent number: 10971417
    Abstract: Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Sen Lu, Wen-Chih Chiou, Wen-Ching Tsai
  • Publication number: 20210090906
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 25, 2021
    Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Publication number: 20210091084
    Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 25, 2021
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Wen-Chih Chiou, Ming-Fa Chen, Sung-Feng Yeh
  • Publication number: 20210082846
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, an interconnection structure, a through substrate via, an insulating layer, a conductive pillar, a dummy conductive pillar, a passivation layer and a bonding pad. The interconnection structure is disposed over the semiconductor substrate. The through substrate via at least partially extends in the semiconductor substrate along a thickness direction of the semiconductor substrate, and electrically connects to the interconnection structure. The insulating layer is disposed over the interconnection structure. The conductive pillar is disposed in the insulating layer, and electrically connected to the through substrate via. The dummy conductive pillar is disposed in the insulating layer, and laterally separated from the conductive pillar. The passivation layer is disposed over the insulating layer.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chi Lin, Chen-Hua Yu, Tsang-Jiuh Wu, Wen-Chih Chiou