Patents by Inventor Wen-Chih Chiou

Wen-Chih Chiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bonding apparatus and method of bonding substrates
    Patent number: 10872874
    Abstract: A bonding apparatus includes a chuck and a bonding head. The chuck is configured to carry a plurality of substrates to be bonded. The bonding head has a cavity facing the chuck and includes a divider, at least one pneumatic component and a diaphragm. The divider is disposed in the cavity and dividing the cavity into a plurality of compartments. The at least one pneumatic component is disposed in at least one of the compartments. The diaphragm covers the cavity and is disposed between the at least one pneumatic component and the chuck.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: December 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ebin Liao, Wen-Chih Chiou
  • INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
    Publication number: 20200395338
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Die structure, die stack structure and method of fabricating the same
    Patent number: 10867943
    Abstract: Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou, Tung-Hsien Wu
  • Method and structure of three-dimensional chip stacking
    Patent number: 10867985
    Abstract: A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Yung-Chi Lin
  • Die stack structure and method of fabricating the same
    Patent number: 10867963
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Method and apparatus for bonding semiconductor devices
    Patent number: 10867831
    Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
  • 3D packages and methods for forming the same
    Patent number: 10854567
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou, Shin-Puu Jeng, Bruce C. S. Chou
  • Forming metal bonds with recesses
    Patent number: 10854574
    Abstract: A method includes forming a first device die, which includes depositing a first dielectric layer, and forming a first metal pad in the first dielectric layer. The first metal pad includes a recess. The method further includes forming a second device die including a second dielectric layer and a second metal pad in the second dielectric layer. The first device die is bonded to the second device die, with the first dielectric layer being bonded to the second dielectric layer, and the first metal pad being bonded to the second metal pad.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Wen-Chih Chiou
  • Method and Apparatus for Bonding Semiconductor Devices
    Publication number: 20200373185
    Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
  • Embedded 3D interposer structure
    Patent number: 10847414
    Abstract: A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ching Shih, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng, Chen-Hua Yu
  • Through Via Structure and Method
    Publication number: 20200343176
    Abstract: A method comprises forming a trench extending through an interlayer dielectric layer over a substrate and partially through the substrate, depositing a photoresist layer over the trench, wherein the photoresist layer partially fills the trench, patterning the photoresist layer to remove the photoresist layer in the trench and form a metal line trench over the interlayer dielectric layer, filling the trench and the metal line trench with a conductive material to form a via and a metal line, wherein an upper portion of the trench is free of the conductive material and depositing a dielectric material over the substrate, wherein the dielectric material is in the upper portion of the trench.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Yung-Chi Lin, Hsin-Yu Chen, Lin-Chih Huang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Interconnect structure and method of forming same
    Patent number: 10811374
    Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Alignment Marks in Substrate Having Through-Substrate Via (TSV)
    Publication number: 20200321249
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Semiconductor package
    Patent number: 10797031
    Abstract: A semiconductor package includes a first optical transceiver, a second optical transceiver, a third optical transceiver, and a plasmonic waveguide. The first optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The second optical transceiver is stacked on the first optical transceiver. The third optical transceiver includes at least one optical input/output portion for transmitting and receiving optical signal. The third optical transceiver is stacked on the second optical transceiver. The plasmonic waveguide penetrates through the second optical transceiver and optically couples the at least one optical input/output portion of the first optical transceiver and the at least one optical input/output portion of the third optical transceiver.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kuang Liao, Cheng-Chun Tsai, Chen-Hua Yu, Fang-Cheng Chen, Wen-Chih Chiou, Ping-Jung Wu
  • Method of making a semiconductor component having through-silicon vias
    Patent number: 10784162
    Abstract: A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Cheng-Hung Chang, Ebin Liao, Chia-Lin Yu, Hsiang-Yi Wang, Chun Hua Chang, Li-Hsien Huang, Darryl Kuo, Tsang-Jiuh Wu, Wen-Chih Chiou
  • PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20200294966
    Abstract: The disclosure provides a method of forming a package structure, and the method includes: bonding a die to a wafer; performing a thinning process on the die, wherein the die has a first total thickness variation (TTV) after performing the thinning process; forming a dielectric layer on the wafer to cover sidewalls and a top surface the die; performing a first removal process to remove a first portion of the dielectric layer and expose the top surface of the die; and performing a second removal process to remove a second portion of the dielectric layer and a portion of the die, wherein after performing the second removal process, the die has a second TTV less than the first TTV.
    Type: Application
    Filed: May 31, 2020
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Ebin Liao, Hong-Ye Shih, Wen-Chih Chiou, Jia-Ling Ko
  • DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20200294965
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE STRUCTURE
    Publication number: 20200286879
    Abstract: A method of manufacturing a semiconductor package structure includes: bonding a die to a wafer; forming a dielectric material layer on the wafer to cover a top surface and sidewalls of the die; performing a removal process to remove a portion of the dielectric material layer, so as to at least expose a portion of the top surface of the die, wherein the dielectric material layer comprises a protruding part over the top surface of the die after performing the removal process; and performing a planarization process to planarize top surfaces of the die and the dielectric material layer, and thereby forming a dielectric layer laterally aside the die.
    Type: Application
    Filed: May 25, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Method and apparatus for bonding semiconductor devices
    Patent number: 10748803
    Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
  • Via for Semiconductor Device Connection and Methods of Forming the Same
    Publication number: 20200243442
    Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.
    Type: Application
    Filed: April 13, 2020
    Publication date: July 30, 2020
    Inventors: Chen-Hua Yu, An-Jhih Su, Chi-Hsi Wu, Wen-Chih Chiou, Tsang-Jiuh Wu, Der-Chyang Yeh, Ming Shih Yeh