Patents by Inventor Wen-Chih Yang
Wen-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096847Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang, Ming-Tsu Chung
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Publication number: 20240090230Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.Type: ApplicationFiled: January 9, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11911951Abstract: A matte film for hot pressing and a manufacturing method thereof are provided. The manufacturing method includes steps of forming at least one polyester composition into an unstretched polyester thick film and stretching the unstretched polyester thick film in a machine direction (MD) and a transverse direction (TD). The polyester composition includes 81% to 97.9497% by weight of a polyester resin, 0.02% to 2% by weight of an antioxidative ingredient, 0.0003% to 1% by weight of a nucleating agent, 0.01% to 2% by weight of a flow aid, 0.01% to 2% by weight of a polyester modifier, 0.01% to 2% by weight of an inorganic filler, and 2% to 10% by weight of silica particles. The polyester resin has an intrinsic viscosity between 0.60 dl/g and 0.80 dl/g.Type: GrantFiled: September 4, 2020Date of Patent: February 27, 2024Assignee: NAN YA PLASTICS CORPORATIONInventors: Te-Chao Liao, Wen-Cheng Yang, Wen-Jui Cheng, Chia-Yen Hsiao, Chien-Chih Lin
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Patent number: 9307602Abstract: An illumination system for a projection apparatus includes a light source module, an integrating rod and an optical detecting module. The light source module is capable of emitting an illuminating light beam. The integrating rod has a light entrance surface facing toward the light source module. The optical detecting module includes a light guiding device and an optical detecting device. The light guiding device has a first end surface and a second end surface. The first end surface is farther away from the light entrance surface of the integrating rod than the second end surface. The optical detecting device is disposed adjacent to the first end surface of the light guiding device and electrically connected to the light source module. The light source module is capable of adjusting intensity of the illuminating light beam according to randomly emitted light detected by the optical detecting device.Type: GrantFiled: October 25, 2013Date of Patent: April 5, 2016Assignee: CORETRONIC CORPORATIONInventors: Wen-Chih Yang, Yung-Ta Chen, Sheng-Yu Chiu, Fan-Chieh Chang
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Patent number: 8728900Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.Type: GrantFiled: October 11, 2012Date of Patent: May 20, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Mong-Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li
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Publication number: 20140117857Abstract: An illumination system for a projection apparatus includes a light source module, an integrating rod and an optical detecting module. The light source module is capable of emitting an illuminating light beam. The integrating rod has a light entrance surface facing toward the light source module. The optical detecting module includes a light guiding device and an optical detecting device. The light guiding device has a first end surface and a second end surface. The first end surface is farther away from the light entrance surface of the integrating rod than the second end surface. The optical detecting device is disposed adjacent to the first end surface of the light guiding device and electrically connected to the light source module. The light source module is capable of adjusting intensity of the illuminating light beam according to randomly emitted light detected by the optical detecting device.Type: ApplicationFiled: October 25, 2013Publication date: May 1, 2014Applicant: CORETRONIC CORPORATIONInventors: Wen-Chih YANG, Yung-Ta CHEN, Sheng-Yu CHIU, Fan-Chieh CHANG
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Patent number: 8450161Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: May 7, 2012Date of Patent: May 28, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8294216Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.Type: GrantFiled: August 14, 2008Date of Patent: October 23, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Harry Chuang, Mong Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li
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Publication number: 20120225529Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: May 7, 2012Publication date: September 6, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chieh-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Patent number: 8193586Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: GrantFiled: February 20, 2009Date of Patent: June 5, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
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Patent number: 8003467Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: GrantFiled: April 30, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Patent number: 7915111Abstract: An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions.Type: GrantFiled: August 8, 2007Date of Patent: March 29, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Lee, Harry Chuang
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Publication number: 20100109088Abstract: The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.Type: ApplicationFiled: April 30, 2009Publication date: May 6, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jin-Aun Ng, Wen-Chih Yang, Chien-Liang Chen, Chung-Hau Fei, Maxi Chang, Bao-Ru Young, Harry Chuang
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Publication number: 20100052072Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region.Type: ApplicationFiled: February 9, 2009Publication date: March 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chii-Horng Li, Po-Nien Chen, Chung-Hau Fei, Chien-Liang Chen, Wen-Chih Yang, Harry Chuang
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Publication number: 20100044803Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.Type: ApplicationFiled: February 20, 2009Publication date: February 25, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
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Publication number: 20100038692Abstract: An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode.Type: ApplicationFiled: August 14, 2008Publication date: February 18, 2010Inventors: Harry Chuang, Mong Song Liang, Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Li
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Patent number: 7655984Abstract: A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode.Type: GrantFiled: June 12, 2007Date of Patent: February 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Liang Chen, Wen-Chih Yang, Chii-Horng Li, Harry Chuang
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Publication number: 20090039433Abstract: An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Chih Yang, Chien-Liang Chen, Chii-Horng Lee, Harry Chuang
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Publication number: 20080308873Abstract: A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode.Type: ApplicationFiled: June 12, 2007Publication date: December 18, 2008Inventors: Chien-Liang Chen, Wen-Chih Yang, Chii-Horng Li, Harry Chuang
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Patent number: 7061117Abstract: A bump layout on the active region of a driver IC for increasing overall bump count. The layout fits IC packages that have a narrow and long body profile. Bumps are positioned close to the long side and central regions of the active region so that low marking pressure on the shorter sides of the package during chip-glass bondage is avoided. Dummy bumps may also be positioned close to the shorter sides of the package so that pressure distribution is optimized during chip-glass bondage.Type: GrantFiled: March 18, 2004Date of Patent: June 13, 2006Assignee: Au Optronics CorporationInventors: Wen-Chih Yang, Feng-Cheng Su, Chin-Chen Yang