Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.

Abstract: Disclosed herein is a transparent optical element for changing a propagation direction of light. The transparent optical element includes a light-receiving surface and a light-emitting surface. The light-receiving surface is formed thereon with a first recess having a bottom surface and a second recess located thereon. The second recess has a lateral surface connected to the bottom surface such that a first angle of about 90 degrees to less than 180 degrees is formed between the bottom surface and the lateral surface. An indicator light comprising the transparent optical element is also disclosed.

Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.

Abstract: An address buffer for high speed static random-access-memory (SRAM) devices is disclosed. The address buffer includes a buffer stage, an out-phase variable buffer circuit and an in-phase variable buffer circuit. The buffer stage includes a number of series-connected buffer units for transmitting an input address signal. The out-phase variable buffer circuit is connected to the buffer stage for providing a first buffer condition in a write period and for providing a second buffer condition in a read period. The in-phase variable buffer circuit is also connected to the buffer stage for providing a third buffer condition in the write period and for providing a fourth buffer condition in the read period. An external address signal can be delayed by the various buffer conditions of the address buffer during the write period to optimize the operation of the SRAM devices, and the various buffer conditions will not affect the read period.