Patents by Inventor Wen-Ching Hsu

Wen-Ching Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015143
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Application
    Filed: September 18, 2024
    Publication date: January 9, 2025
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Patent number: 12163247
    Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: December 10, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Patent number: 12119382
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: October 15, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Patent number: 12037696
    Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: July 16, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Patent number: 12037697
    Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.
    Type: Grant
    Filed: May 30, 2023
    Date of Patent: July 16, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Patent number: 11923422
    Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 5, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ming-Shien Hu, Chien-Jen Sun, I-Ching Li, Wen-Ching Hsu
  • Patent number: 11859965
    Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: January 2, 2024
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Wen-Ching Hsu, Chia-Chi Tsai, I-Ching Li
  • Publication number: 20230304185
    Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Publication number: 20230295833
    Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 21, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Publication number: 20230282472
    Abstract: A wafer and a wafer processing method are included. The wafer processing method includes the following steps. A wafer is provided having a first surface and a second surface opposite to the first surface. A fixture pattern is pasted on the first surface to cover a first portion of the first surface of the wafer, and a second portion of the first surface is exposed by the fixture pattern. A first etching step is performed on the second portion of the first surface to form a first etching pattern on the first surface of the wafer. The fixture pattern is removed from the first surface, and the second surface of the wafer is ground.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 7, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Wen-Huai Yu, Shih-Che Hung, Hung-Chang Lo, Chun-I Fan, Chia-Chi Tsai, Wen-Ching Hsu
  • Patent number: 11708642
    Abstract: A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 25, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-Hung Chen, Hsing-Pang Wang, Wen-Ching Hsu, I-Ching Li
  • Patent number: 11705489
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 18, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Publication number: 20230215924
    Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.
    Type: Application
    Filed: March 9, 2023
    Publication date: July 6, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, Manhsuan Lin
  • Patent number: 11688628
    Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: June 27, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chi-Tse Lee, Chun-I Fan, Wen-Ching Hsu
  • Publication number: 20230160095
    Abstract: A method for producing Si ingot single crystal including a Si ingot single crystal growing step, a temperature gradient controlling step and a continuous growing step is provided. In the growing step, the Si ingot single crystal is grown in silicon melt in crucible, and the growing step includes providing a low-temperature region in the Si melt and providing a silicon seed to contact the melt surface of the silicon melt to start crystal growth, and silicon single crystal grows along the melt surface of the silicon melt and toward the inside of the silicon melt. In the temperature gradient controlling step, the under-surface temperature gradient of the silicon single crystal is G1, the above-surface temperature gradient of the silicon single crystal is G2, G1 and G2 satisfy: G2/G1<6. The step of controlling the temperature gradient of silicon single crystal is repeated to obtain the Si ingot single crystal.
    Type: Application
    Filed: October 12, 2022
    Publication date: May 25, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Kazuo Nakajima, Masami Nakanishi, Yu Sheng Su, Wen-Ching Hsu
  • Publication number: 20230052218
    Abstract: Provided is a method of SiC wafer processing, and the method includes the following steps. A SiC wafer is provided, and the SiC wafer has a first surface and an opposing second surface. A fine grinding process is performed on the first surface and the second surface of the SiC wafer. A dry etching process is performed on the first surface and the second surface of the SiC wafer to make the roughness of the first surface and the second surface 2.5 nm or less. After the dry etching process, a polishing process is performed on the first surface and the second surface of the SiC wafer.
    Type: Application
    Filed: July 11, 2022
    Publication date: February 16, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Shih-Che Hung, Wen-Huai Yu, Wen-Ching Hsu
  • Patent number: 11538681
    Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (?) and 500 angstroms.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 27, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chun-I Fan, Wen-Ching Hsu
  • Publication number: 20220357152
    Abstract: A material analysis method is provided. A plurality of wafers processed from a plurality of ingots are measured by a measuring instrument to obtain an average of a bow of each of the wafers processed from the ingots and a plurality of full widths at half maximum (FWHM) of each of the wafers. Key factors respectively corresponding to the ingots are calculated according to the FWHM of the wafers. A regression equation is obtained according to the key factors and the average of the bows.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 10, 2022
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Shang-Chi Wang, Wen-Ching Hsu, Chia-Chi Tsai, I-Ching Li
  • Patent number: 11377752
    Abstract: A mono-crystalline silicon growth method includes: providing a furnace, a supporting base and a crucible which do not rotate relative to the furnace, and a heating module disposed at an outer periphery of the supporting base. After solidifying a liquid surface of a silicon melt in the crucible to form a crystal, the heating power of the heating module is successively reduced to appropriately adjust the temperature around the crucible to effectively control a temperature gradient of a thermal field around the crucible, so as to form a mono-crystalline silicon ingot by solidifying the silicon melt.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 5, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-Hung Chen, Hsing-Pang Wang, Wen-Ching Hsu, I-Ching Li
  • Patent number: 11326272
    Abstract: A mono-crystalline silicon growth apparatus includes a furnace, a support base, a crucible, a heating module disposed outside of the crucible, and a heat adjusting module above the crucible. The heat adjusting module includes a diversion tube, a plurality of heat preservation sheets, and a hard shaft. The diversion tube includes a tube body and a carrying body connected to the tube body. The heat preservation sheets are sleeved around the tube body and are stacked and disposed on the carrying body. The hard shaft passes through the tube body and does not rotate. The hard shaft includes a water flow channel disposed therein and a clamping portion configured to clamp a seed crystal. Therefore, a fluid injected into the water flow channel takes away the heat near the clamping portion. A heat adjusting module and a hard shaft of the mono-crystalline silicon growth apparatus are provided.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 10, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-Hung Chen, Hsing-Pang Wang, Wen-Ching Hsu, I-Ching Li