Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A chip package includes: a substrate having a first and a second surface; a device region and a pad disposed on the first surface; a hole extending from the second surface to the pad; an insulating layer located on a sidewall of the hole; a carrier substrate located on the second surface; a first redistribution layer located between the carrier substrate and the insulating layer and located in the hole to electrically contact with the pad, wherein an edge of the first redistribution layer is exposed on a sidewall formed by the carrier substrate and the insulating layer; a second redistribution layer located on the carrier substrate, extending towards the second surface, and contacting the exposed edge of the first redistribution layer; and a buffer layer located on or below the second surface of the substrate and located between the second redistribution layer and the substrate.

Abstract: A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.

Abstract: Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.

Abstract: A method for fabricating a contact hole is provided. A semiconductor substrate having thereon a conductive region is prepared. A dielectric layer is deposited on the semiconductor substrate and the conductive region. An etching resistive layer is coated on the dielectric layer. A silicon-containing hard mask bottom anti-reflection coating (SHB) layer is then coated on the etching resistive layer. A photoresist layer is then coated on the SHB layer. A lithographic process is performed to form a first opening in the photoresist layer. Using the photoresist layer as a hard mask, the SHB layer is etched through the first opening, thereby forming a shrunk, tapered second opening in the SHB layer. Using the etching resistive layer as an etching hard mask, etching the dielectric layer through the second opening to form a contact hole in the dielectric layer.

Abstract: Automatic process control of after-etch-inspection critical dimension. A dielectric layer is deposited over a substrate and is then planarized to a first thickness. A cap oxide layer having a second thickness is deposited, wherein the combination of the first thickness and the second thickness is substantially constant. An ADI CD of a contact hole to be formed on the substrate is altered and pre-determined based on the second thickness of the cap oxide layer. A photoresist layer is formed on the cap oxide layer. An opening having the predetermined ADI CD is formed in the photoresist layer. Using the photoresist layer as an etching mask, the cap oxide layer and the dielectric layer is etched through the opening to form a contact hole having an AEI CD.

Abstract: A method for forming a contact opening is described. A substrate formed with a semiconductor device thereon is provided, and then an etch stop layer, a dielectric layer and a patterned photoresist layer are formed sequentially over the substrate. The exposed dielectric layer and 20% to 90% of the thickness of the exposed etch stop layer are removed to form an opening. After the patterned photoresist layer is removed, an etch step using a reaction gas is conducted to remove the etch stop layer remaining at the bottom of the opening and form a contact opening that exposes a part of the device, wherein the reaction gas is selected from CF4, CHF3 and CH2F2. By using the method, a micro-masking effect is avoided, and oxidation at the bottom of the contact opening conventionally caused by the photoresist removal using oxygen plasma is also avoided.