Patents by Inventor Wen Chu Huang

Wen Chu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199033
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Wei-Chun Hua, Wen-Chu Huang, Yen-Yu Chen, Che-Chih Hsu, Chinyu Su, Wen Han Hung
  • Patent number: 12087627
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20230223335
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: March 7, 2023
    Publication date: July 13, 2023
    Inventors: Hung Hsun LIN, Wei-Chun HUA, Wen-Chu HUANG, Yen-Yu CHEN, Che-Chih HSU, Chinyu SU, Wen Han HUNG
  • Patent number: 11616013
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20220367343
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 17, 2022
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Publication number: 20210391251
    Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Hung Hsun Lin, Che-Chih Hsu, Wen-Chu Huang, Chinyu Su, Yen-Yu Chen, Wei-Chun Hua, Wen Han Hung
  • Patent number: 6743690
    Abstract: A method of forming a metal-oxide semiconductor (MOS) transistor. A semiconductor substrate is provided. A polysilicon layer is then deposited on the semiconductor substrate. The polysilicon layer is selectively etched to form a gate electrode. A silicon oxide layer is grown on the top and the sidewall. Ions (or dopants) are doped into the semiconductor substrate to form a lightly doped region. Then, a nitride spacer is formed on the sidewall of the silicon oxide layer. Finally, ions are doped into the semiconductor substrate to form a heavily doped region to serve as a source/drain of the MOS transistor.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: June 1, 2004
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Tzu-Kun Ku, Wen-Chu Huang
  • Publication number: 20040048438
    Abstract: A method of forming a metal-oxide semiconductor (MOS) transistor. A semiconductor substrate is provided. A polysilicon layer is then deposited on the semiconductor substrate. The polysilicon layer is selectively etched to form a gate electrode. A silicon oxide layer is grown on the top and the sidewall. Ions (or dopants) are doped into the semiconductor substrate to form a lightly doped region. Then, a nitride spacer is formed on the sidewall of the silicon oxide layer. Finally, ions are doped into the semiconductor substrate to form a heavily doped region to serve as a source/drain of the MOS transistor.
    Type: Application
    Filed: September 10, 2002
    Publication date: March 11, 2004
    Inventors: Tzu-Kun Ku, Wen-Chu Huang
  • Patent number: 6538186
    Abstract: A music box container, comprising a box unit, a cover unit, a sound-emitting device, a transmission mechanism and a moving picture, wherein the transmission mechanism is installed in the box unit and the cover unit. The transmission mechanism includes a gear set and a connecting-rod mechanism. The gear set is joined between the sound-emitting device and the connecting-rod mechanism. The moving picture includes a frame unit and a plurality of moving objects. The frame unit is accommodated inside the cover unit. The moving objects are installed inside the frame unit and are connected with the connecting-rod mechanism. Thereby, the components include a music box container with a plurality of moving objects that swing leftward, rightward, upward, and downward.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: March 25, 2003
    Inventor: Wen Chu Huang