Patents by Inventor Wen-Chuan Chang
Wen-Chuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Patent number: 11945885Abstract: A vinyl-containing copolymer is copolymerized from (a) first compound, (b) second compound, and (c) third compound. (a) First compound is an aromatic compound having a single vinyl group. (b) Second compound is polybutadiene or polybutadiene-styrene having side vinyl groups. (c) Third compound is an acrylate compound. The vinyl-containing copolymer includes 0.003 mol/g to 0.010 mol/g of benzene ring, 0.0005 mol/g to 0.008 mol/g of vinyl group, and 1.2*10?5 mol/g to 2.4*10?4 mol/g of ester group.Type: GrantFiled: December 29, 2022Date of Patent: April 2, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Po Kuo, Shin-Liang Kuo, Shu-Chuan Huang, Yan-Ting Jiang, Jian-Yi Hang, Wen-Sheng Chang
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Patent number: 11935947Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.Type: GrantFiled: October 8, 2019Date of Patent: March 19, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Shin-Chuan Huang, Wen-Jung Liao, Chun-Liang Hou
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Patent number: 11937415Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.Type: GrantFiled: July 27, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
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Publication number: 20190384117Abstract: A display device is provided, including a panel, a plurality of first light sources, and a plurality of second light sources. The panel includes a first display area and a second display area. The first light sources correspond to the first display area. The second light sources correspond to the second display area. The color of the second light sources is different from the color of the first light sources. When the brightness of the second light sources is increased, the brightness of the first light sources decreases, and when the brightness of the first light sources is increased, the brightness of the second light sources decreases.Type: ApplicationFiled: August 27, 2019Publication date: December 19, 2019Inventors: Wen-Jyh SAH, Wen-Chuan CHANG
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Patent number: 9583641Abstract: A manufacturing method of a semiconductor device includes the following steps. A plurality of select gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between the two adjacent select gates. An insulation block is formed between the two charge storage structures and formed on the source region. A memory gate is formed on the insulation block, and the memory gate is connected to the two charge storage structures.Type: GrantFiled: December 7, 2015Date of Patent: February 28, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yuan-Hsiang Chang, Yi-Shan Chiu, Chih-Chien Chang, Jianjun Yang, Wen-Chuan Chang
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Publication number: 20160109756Abstract: A display device is provided, including a panel, a plurality of first light sources, and a plurality of second light sources. The panel includes a first display area and a second display area. The first light sources correspond to the first display area. The second light sources correspond to the second display area. The color of the second light sources is different from the color of the first light sources. When the brightness of the second light sources is increased, the brightness of the first light sources decreases, and when the brightness of the first light sources is increased, the brightness of the second light sources decreases.Type: ApplicationFiled: October 20, 2015Publication date: April 21, 2016Inventors: Wen-Jyh SAH, Wen-Chuan CHANG
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Patent number: 8958245Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.Type: GrantFiled: May 29, 2012Date of Patent: February 17, 2015Assignee: eMemory Technology Inc.Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
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Publication number: 20120236646Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.Type: ApplicationFiled: May 29, 2012Publication date: September 20, 2012Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang