Abstract: The invention discloses a superconductor-metal conductive material, comprising a metal powder, a superconductor powder and an organic carrier adhesive, wherein the metal powder has 50-95 wt % of a total weight of said metal powder, said superconductor powder and said organic carrier binder, the superconductor powder has 4-40 wt % of said total weight, and the organic carrier binder has 1-10 wt % of said total weight, wherein the superconductor powder comprises one or more mixtures of La2-x-ySrxBayCuO4, La2-x-y BixSryCuO4, La2-x-y-z BixSryCaZCuO4, La2-x-y-z HgxBayCazCuO4, La2-x-ySrxTlyBazCuO6, La2-x-y-z-wSrxTlyBazCawCu2O8, and HgBa2Ca2Cu3O8, where each of x, y, z, and w is between 0.1 and 0.9.

Abstract: A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.

Abstract: The present invention relates to a porous lithium phosphate metal salt and method for preparing the same. The method includes the following steps, which comprises: (A) providing starting materials including a phosphate-containing precursor, a lithium-containing precursor, a metal source, and a carbon source; (B) grinding the starting materials at room temperature to obtain a mixture; (C) spray-granulating the mixture to form a granular mixture; and (D) sintering the granular mixture to obtain a porous lithium phosphate metal salt, wherein the spray granulation process in the step (C) uses a spray granulation device having a plurality of spray nozzles.

Abstract: Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages.

Abstract: Disclosed is a mold array process (MAP) method to encapsulate cut edges of substrate units. A substrate strip includes a plurality of substrate units arranged in a matrix. Scribe lines are defined between adjacent substrate units and at the peripheries of the matrix where pre-cut grooves are formed along the scribe lines with a width greater than the width of the scribe lines. An encapsulant is formed on the matrix of the substrate strip to continuously encapsulate the substrate units and the scribe lines to enable the encapsulant to fill into the pre-cut grooves to further encapsulate the cut edges of the substrate units. The cut edges of the substrate units are still encapsulated by the encapsulant even after singulation processes where substrate units are singulated into individual semiconductor packages to prevent the exposure of the plated traces of the substrate units to enhance the moisture resistance capability of the semiconductor packages.

Abstract: Disclosed is a mold array process (MAP) method to prevent exposure of peripheries of substrate units where the major characteristic is to implement two kinds of encapsulating materials in the MAP method in mass production. A first encapsulating material for encapsulating chips is formed on a substrate strip by molding to continuously encapsulate the substrate units and the scribe lines between adjacent substrate units. Prior to forming a second encapsulating material, a plurality of cut grooves are formed along the scribing lines by pre-cutting processes to penetrate through the substrate strip but without penetrating through the first encapsulating material and have such a width that a plurality of peripheries of the substrate units are exposed outside the scribing lines. Then, the second encapsulating material is filled into the cut grooves.

Abstract: A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a FOW (film over wire) adhesive is formed on a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.

Abstract: Disclosed is a flip-chip bonding method to reduce voids in underfill material. A substrate with connecting pads is provided. At least a chip with a plurality of bumps is bonded on the substrate and then an underfill material is formed between the chip and the substrate. Finally, the substrate is placed in a pressure oven in which a positive pressure greater than one atm is provided, meanwhile, the underfill material is thermally cured with exerted pressures to reduce bubbles or voids trapped inside the underfill material to avoid popcorn issues due to CTE mismatch between the chip and the substrate. In one embodiment, another underfill material is further formed between a plurality of chips and bubbles or voids trapped between the chips are also reduced by the pressurized curing.

Abstract: A multi-chip stacking method to reduce voids between stacked chips is revealed. A first chip is disposed on a substrate, and a plurality of first bonding wires are formed by wire bonding to electrically connect the first chip and the substrate. A second chip is disposed on an active surface of the first chip where a dielectric layer and a FOW adhesive (film over wire) adhesive are attached onto a back surface of the second chip. The FOW adhesive partially encapsulates the first bonding wires and adheres to the active surface of the first chip. Then, the substrate is placed in a pressure oven to provide a positive pressure greater than one atm during thermally curing the FOW adhesive with exerted pressures. Accordingly, voids can be reduced inside the FOW adhesive during the multi-chip stacked processes where issues of poor adhesion and popcorn between chips can be avoided.

Abstract: A discharge lamp is disclosed, including a sealed vessel with an inner surface, at least one illuminating gas filled inside the sealed vessel, and a fluorescent layer coated on the inner surface. The composition of the fluorescent layer is adjusted according to a colored light emitted by the illuminating gas during a discharge process within the sealed vessel, such that the colored light is converted into a visible light after passing through the fluorescent layer.

Abstract: A window-type semiconductor package is revealed, primarily comprising a substrate with an interconnection channel, a chip on the substrate, a die-attach adhesive between the chip and the substrate, and an encapsulant filling the interconnection channel. A first solder mask formed on the top surface of the substrate has a specific pattern. The die-attach adhesive bonds the active surface of the chip to the first solder mask with the bonding pads of the chip aligned inside the interconnection channel. The first solder mask has an opening to expose the interconnection channel and further to form an indentation from the interconnection channel to expose the top surface to prevent damaging of the active surface of the chip adjacent to the edges of the interconnection channel to ensure the integrity and yield of the final products.

Abstract: This invention relates to method(s) of fabricating electrodes of an external electrode fluorescence lamp (EEFL) for use in thin film transistor-liquid crystal display (TFT-LCD) applications. Also disclosed is a structure with electrodes for external electrode fluorescence lamps used in TFT-LCD backlight units.

Abstract: A discharge lamp is disclosed, including a sealed vessel with an inner surface, at least one illuminating gas filled inside the sealed vessel, and a fluorescent layer coated on the inner surface. The composition of the fluorescent layer is adjusted according to a colored light emitted by the illuminating gas during a discharge process within the sealed vessel, such that the colored light is converted into a visible light after passing through the fluorescent layer.

Abstract: A card-type memory package is revealed, primarily comprising a substrate, a plurality of gold fingers, at least a memory chip, an LED chip, and an encapsulant. The memory chip and the LED chip are disposed on an encapsulated surface of the substrate with the LED chip adjacent to a rear side of the substrate. The gold fingers are attached to the substrate adjacent to a front side of the substrate. The encapsulant is formed on the encapsulated surface to encapsulate the memory chip and the LED chip with the gold fingers exposed. Therefore, the card-type memory package has the LED indication of reading and writing information with simplified assembling processes.

Abstract: This invention relates to method(s) of fabricating electrodes of an external electrode fluorescence lamp (EEFL) for use in thin film transistor-liquid crystal display (TFT-LCD) applications. Also disclosed is a structure with electrodes for external electrode fluorescence lamps used in TFT-LCD backlight units.