Patents by Inventor Wen-Chun KENG
Wen-Chun KENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937415Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.Type: GrantFiled: July 27, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
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Patent number: 11908860Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.Type: GrantFiled: February 16, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
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Publication number: 20230317522Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.Type: ApplicationFiled: June 8, 2023Publication date: October 5, 2023Applicant: Taiwan Semiconductor Manufacturing Company., Ltd.Inventors: Wen-Chun KENG, Yu-Kuan LIN, Chang-Ta YANG, Ping-Wei WANG
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Patent number: 11710663Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first fin structure, a second fin structure, and a third fin structure over the semiconductor substrate. The semiconductor device structure also includes a merged semiconductor element on the first fin structure and the second fin structure and an isolated semiconductor element on the third fin structure. The semiconductor device structure further includes an isolation feature over the semiconductor substrate and partially or completely surrounding the first fin structure, the second fin structure, and the third fin structure. A top surface of the first fin structure is below a top surface of the isolation feature, and a top surface of the third fin structure is above the top surface of the isolation feature.Type: GrantFiled: March 8, 2021Date of Patent: July 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chun Keng, Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
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Publication number: 20230225098Abstract: A method includes forming a first fin protruding from a substrate in a first region of the substrate and a second fin protruding from the substrate in a second region of the substrate, recessing a portion of the first fin, thereby forming a first recess, recessing a portion of the second fin, thereby forming a second recess, depositing a blocking layer in the second recess, growing a base epitaxial layer in the first recess, removing the blocking layer from the second recess, and growing a doped epitaxial layer in the first recess and the second recess. The base epitaxial layer is dopant free. The doped epitaxial layer abuts the first fin in the first region and the second fin in the second region.Type: ApplicationFiled: June 4, 2022Publication date: July 13, 2023Inventors: Chih-Chuan Yang, Wen-Chun Keng, Shih-Hao Lin, Hsin-Wen Su, Yu-Kuan Lin, Ping-Wei Wang, Jing-Yi Lin
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Patent number: 11690209Abstract: An integrated circuit device includes a FinFET disposed over a doped region of a first type dopant, wherein the FinFET includes a first fin structure and first source/drain (S/D) features, the first fin structure having a first width; and a fin-based well strap disposed over the doped region of the first type dopant, wherein the fin-based well strap includes a second fin structure and second S/D features, the second fin structure having a second width that is larger than the first width, wherein the fin-based well strap connects the doped region to a voltage.Type: GrantFiled: August 4, 2020Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
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Patent number: 11637109Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.Type: GrantFiled: June 29, 2020Date of Patent: April 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11600625Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.Type: GrantFiled: October 14, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Wen-Chun Keng, Lien Jung Hung, Ping-Wei Wang
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Publication number: 20220416046Abstract: A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.Type: ApplicationFiled: April 15, 2022Publication date: December 29, 2022Inventors: Shang-Rong Li, Shih-Hao Lin, Wen-Chun Keng, Chih-Chuan Yang, Chih-Hsiang Huang, Ping-Wei Wang
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Publication number: 20220367482Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.Type: ApplicationFiled: July 22, 2022Publication date: November 17, 2022Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
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Publication number: 20220367483Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.Type: ApplicationFiled: July 20, 2022Publication date: November 17, 2022Inventors: Chih-Chuan YANG, Chia-Hao PAO, Wen-Chun KENG, Lien Jung HUNG, Ping-Wei WANG
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Publication number: 20220367620Abstract: Semiconductor devices having improved source/drain features and methods for fabricating such are disclosed herein. An exemplary device includes a semiconductor layer stack disposed over a mesa structure of a substrate. The device further includes a metal gate disposed over the semiconductor layer stack and an inner spacer disposed on the mesa structure of the substrate. The device further includes a first epitaxial source/drain feature and a second epitaxial source/drain feature where the semiconductor layer stack is disposed between the first epitaxial source/drain feature and the second epitaxial source/drain feature. The device further includes a void disposed between the inner spacer and the first epitaxial source/drain feature.Type: ApplicationFiled: December 15, 2021Publication date: November 17, 2022Inventors: Chih-Chuan Yang, Wen-Chun Keng, Chong-De Lien, Shih-Hao Lin, Hsin-Wen Su, Ping-Wei Wang
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Publication number: 20220367683Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.Type: ApplicationFiled: September 1, 2021Publication date: November 17, 2022Inventors: Chih-Hsuan Chen, Wen-Chun Keng, Yu-Kuan Lin, Shih-Hao Lin
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Publication number: 20220367481Abstract: A method of forming a semiconductor device includes providing a substrate including a circuit region and a well strap region, forming a mandrel extending from the circuit region to the well strap region, depositing mandrel spacers on sidewalls of the mandrel, removing the mandrel in the circuit region, while the mandrel in the well strap region remains intact, patterning the substrate with the mandrel spacers in the circuit region and the mandrel in the well strap region as an etch mask, thereby forming at least a first fin in the circuit region and a second fin in the well strap region, and epitaxially growing a first epitaxial feature over the first fin in the circuit region and a second epitaxial feature over the second fin in the well strap region. A width of the second fin is larger than a width of the first fin.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Chih-Chuan Yang, Kuo-Hsiu Hsu, Feng-Ming Chang, Wen-Chun Keng, Lien Jung Hung
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Publication number: 20220359026Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Hsin-Wen SU, Kian-Long LIM, Wen-Chun KENG, Chang-Ta YANG, Shih-Hao LIN
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Patent number: 11462282Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.Type: GrantFiled: April 1, 2020Date of Patent: October 4, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Wen Su, Kian-Long Lim, Wen-Chun Keng, Chang-Ta Yang, Shih-Hao Lin
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Publication number: 20220173098Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.Type: ApplicationFiled: February 16, 2022Publication date: June 2, 2022Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
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Publication number: 20220115387Abstract: A semiconductor device and method of fabricating thereof where the device includes a fin structure between a first isolation region and a second isolation region. A first source/drain feature is formed over a recessed portion of the first fin structure. The first source/drain feature interfaces a top surface of the first isolation region for a first distance and interfaces the top surface of the second isolation region for a second distance. The first distance is different than the second distance. The source/drain feature is offset in a direction.Type: ApplicationFiled: October 14, 2020Publication date: April 14, 2022Inventors: Chih-Chuan Yang, Chia-Hao PAO, Wen-Chun Keng, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11257817Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.Type: GrantFiled: March 4, 2020Date of Patent: February 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
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Publication number: 20210408012Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang