Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: A package comprises an interposer, comprising an interposer substrate including at least one layer, and a plurality of RDLs formed through at least a portion of the interposer substrate. The package also includes a die device structure comprising at least one device die, and a first test line (TL) structure interposed between the interposer and the die device structure. The first TL structure includes at least one first test line electrically coupled to the at least one device die, at least a portion of the at least one first test line extending beyond a peripheral edge of the die device structure to provide an electrical interface with the at least one device die.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: A method of manufacturing a piezoelectric ink-jet print-head uses a metallic layer and a thick film layer with a slot hole therein instead of a ceramic vibration plate and an ink layer. The piezoelectric layer and the upper electrode layer are formed inside the ink cavity so that overall thickness of the print head is reduced. To form the ink-jet print head, a metallic layer and a lower electrode layer are sequentially formed over a substrate. A patterned piezoelectric layer and an upper electrode layer are sequentially formed over the lower electrode layer. A patterned thick film layer with a slot hole therein is formed over the metallic layer. The thick film layer and the metallic layer together form a cavity that encloses the piezoelectric layer and the upper electrode layer. A nozzle plate having a nozzle thereon is attached to the thick film layer. The nozzle plate, the thick film layer and the metallic layer together form an ink cavity. The hole in the nozzle is continuous with the ink cavity.

Abstract: A piezoelectric ink-jet printhead that uses a metallic layer and a thick film layer with a slot hole therein instead of a ceramic vibration plate and an ink layer. The piezoelectric layer and the upper electrode layer are formed inside the ink cavity so that overall thickness of the print head is reduced. To form the ink-jet print head, a metallic layer and a lower electrode layer are sequentially formed over a substrate. A patterned piezoelectric layer and an upper electrode layer are sequentially formed over the lower electrode layer. A patterned thick film layer with a slot hole therein is formed over the metallic layer. The thick film layer and the metallic layer together form a cavity that encloses the piezoelectric layer and the upper electrode layer. A nozzle plate having a nozzle thereon is attached to the thick film layer. The nozzle plate, the thick film layer and the metallic layer together form an ink cavity. The hole in the nozzle is continuous with the ink cavity.

Abstract: A piezoelectric ink-jet printhead that uses a metallic layer and a thick film layer with a slot hole therein instead of a ceramic vibration plate and an ink layer. The piezoelectric layer and the upper electrode layer are formed inside the ink cavity so that overall thickness of the print head is reduced. To form the ink-jet print head, a metallic layer and a lower electrode layer are sequentially formed over a substrate. A patterned piezoelectric layer and an upper electrode layer are sequentially formed over the lower electrode layer. A patterned thick film layer with a slot hole therein is formed over the metallic layer. The thick film layer and the metallic layer together form a cavity that encloses the piezoelectric layer and the upper electrode layer. A nozzle plate having a nozzle thereon is attached to the thick film layer. The nozzle plate, the thick film layer and the metallic layer together form an ink cavity. The hole in the nozzle is continuous with the ink cavity.

Abstract: An inkjet printhead chip is installed at the nose of an ink cartridge. Its structure includes a silicon substrate, a barrier layer, and a nozzle plate. The nozzle plate is formed with two parallel rows of inkjet nozzles. Two rows of ink channels roughly parallel to the inkjet nozzles and two rows of independent control circuits are provided among the silicon substrate, the barrier layer and the nozzle plate. The ink channels are disposed between the two rows of nozzles. The control circuits are configured to be on the outer sides of the two rows of nozzles. Using this structure of ink channels and control circuits, the inkjet printhead chip allows a larger area for attaching the nozzle plate. A flexible printed circuit is used to send external control signals from both sides of the chip to the control circuits, starting ink firing elements to eject ink and form patterns or texts on a nearby medium.

Abstract: A piezoelectric ink-jet printhead that uses a metallic layer and a thick film layer with a slot hole therein instead of a ceramic vibration plate and an ink layer. The piezoelectric layer and the upper electrode layer are formed inside the ink cavity so that overall thickness of the print head is reduced. To form the ink-jet print head, a metallic layer and a lower electrode layer are sequentially formed over a substrate. A patterned piezoelectric layer and an upper electrode layer are sequentially formed over the lower electrode layer. A patterned thick film layer with a slot hole therein is formed over the metallic layer. The thick film layer and the metallic layer together form a cavity that encloses the piezoelectric layer and the upper electrode layer. A nozzle plate having a nozzle thereon is attached to the thick film layer. The nozzle plate, the thick film layer and the metallic layer together form an ink cavity. The hole in the nozzle is continuous with the ink cavity.