Patents by Inventor Wen-Chung Shen

Wen-Chung Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145378
    Abstract: An interconnect structure on a semiconductor die includes: a lower conductive layer; an upper conductive layer disposed above the lower conductive layer; and a VIA disposed between the lower conductive layer and the upper conductive layer. The VIA includes: a primary interconnect structure and a sacrificial stress barrier ring disposed around the primary interconnect structure and separated a distance from the primary interconnect structure. A fabrication method for the interconnect structure includes: forming a dielectric layer over a lower conductive layer; patterning photoresist (PR) layer over the dielectric layer to define a location for a plurality of VIA trenches, wherein the patterning includes patterning the PR layer to provide a center opening for the VIA trenches that is surrounded by a ring opening for the VIA trenches, wherein the center opening and the ring opening are spaced apart.
    Type: Application
    Filed: February 7, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ting Liu, Chen-Chiu Huang, Dian-Hau Chen, Hung-Chao Kao, Hsiang-Ku Shen, Wen-Chiung Tu, Li Chung Yu, Yu-Chung Lai
  • Publication number: 20240079263
    Abstract: A wafer container includes a frame, a door and at least a pair of shelves. The frame has opposite sidewalls. The pair of the shelves are respectively disposed and aligned on the opposite sidewalls of the frame. Various methods and devices are provided for holding at least one wafer to the shelves during transport.
    Type: Application
    Filed: February 22, 2023
    Publication date: March 7, 2024
    Inventors: Kai-Hung HSIAO, Chi-Chung JEN, Yu-Chun SHEN, Yuan-Cheng KUO, Chih-Hsiung HUANG, Wen-Chih CHIANG
  • Publication number: 20150301984
    Abstract: A signal decomposition system with low-latency empirical mode decomposition and the method of the same decompose an original signal using iterative computations with different directions of data streams. The directions of data stream in computations of odd or even iterations are adjusted for reducing the number of data stream direction reversals. As a result, computing data can be shared and computing time can be saved. The mechanism helps improve the efficiency of signal decompositions.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 22, 2015
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Wen-Chung SHEN, An-Yeu WU, Hsiao-I JEN
  • Patent number: 5801922
    Abstract: Multi-unit module of portable computer, including a computer housing and a module casing. At least two expansion units are inserted in the module casing as a module. At least one plug is disposed on one side of the module casing and connected to the expansion units. A module insertion slot is disposed on one side of the housing. An inner end of the insertion slot is disposed with at least one socket secured on the main circuit board corresponding to the plug of the module casing, whereby when the module casing is inserted into the insertion slot, the plug is connected with the socket so that the expansion units can be at the same located in the housing and drivingly connected with and controlled by the main circuit board.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: September 1, 1998
    Assignee: Compal Electronics, Inc.
    Inventors: Wen-Chung Shen, Po-An Lin