Patents by Inventor Wen-Chung Yang

Wen-Chung Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250053039
    Abstract: An E-paper display panel including an E-paper display layer, a first substrate, a pixel array layer, a common electrode layer, and a driving circuit is provided. The first substrate is disposed at a first side of the E-paper display layer. The pixel array substrate is disposed between the first substrate and the E-paper display layer and includes touch electrodes and driving pixels arranged in an array. Each driving pixel includes a first pixel electrode and a second pixel electrode. The touch electrodes, the first pixel electrode, and the second pixel electrode are overlapped with each other. The common electrode layer is disposed at a second side of the E-paper display layer. The first side is opposite to the second side. The driving circuit is in signal communication with the common electrode layer and the pixel array layer. The touch electrodes are individually in signal communication with the driving circuit.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 13, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chia-Ming Hsieh, Chi-Mao Hung, Sung-Hui Huang, Chuen-Jen Liu, Liang-Yu Yan, Pei Ju Wu, Po-Chun Chuang, Che-Sheng Chang, Wen-Chung Yang
  • Patent number: 11637017
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: April 25, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Publication number: 20220336621
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Patent number: 11424340
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: August 23, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Publication number: 20220037503
    Abstract: Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.
    Type: Application
    Filed: September 13, 2020
    Publication date: February 3, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Patent number: 11063156
    Abstract: A memory device and a manufacturing method of the memory device are provided. The manufacturing method includes steps below. A plurality of stack structures including a tunneling dielectric layer and a floating gate are formed on a substrate. A liner material layer including a nitride liner layer is formed on the substrate. A top surface of the nitride liner layer is lower than a top surface of the floating gate and is higher than a top surface of the tunneling dielectric layer. An isolation material layer covering the liner material layer is formed on the substrate. The isolation material layer is oxidized, and a portion of the isolation material layer is removed to form an isolation structure. An inter-gate dielectric layer covering the stack structures and the isolation structure is formed on the substrate. A control gate covering the inter-gate dielectric layer is formed on the substrate.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: July 13, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Wen Chung Yang, Shih Hsi Chen, Wei-Chang Lin
  • Publication number: 20160336431
    Abstract: A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 17, 2016
    Inventors: Wen-Chung Yang, Te-Yuan Yin, Ssu-Ting Wang
  • Patent number: 9490349
    Abstract: A method of manufacturing a semiconductor device, which includes the steps of forming a gate stack structure made up of a floating gate, an inter-poly dielectric, a control gate and a metal layer on a substrate, forming a conformal liner on the gate stack structure, covering a mask layer on the liner, where the mask layer is lower than the metal layer so that a portion of the liner is exposed, and performing a nitridation treatment to transform the exposed liner into a nitrided liner, so that at least the portion of the metal layer in the gate stack structure is covered by the nitrided liner.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: November 8, 2016
    Assignee: Powerchip Technology Corporation
    Inventors: Wen-Chung Yang, Te-Yuan Yin, Ssu-Ting Wang