Patents by Inventor Wen Chung

Wen Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9450789
    Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei
  • Publication number: 20160264617
    Abstract: Disclosed herein is an integrated approach to purification process development and execution, including processes comprising particular capture and fine purification steps; processes that employ of a minimal number of buffer systems, and processes that make use of minimally-corrosive buffer systems, as well as combinations thereof.
    Type: Application
    Filed: October 14, 2015
    Publication date: September 15, 2016
    Inventors: Diane D. Dong, Stephen M. Lu, Natarajan Ramasubramanyan, Wen-Chung Lim
  • Patent number: 9437257
    Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Yue-Der Chih, Chan-Hong Chern, Tao Wen Chung
  • Publication number: 20160231771
    Abstract: A display equipment connected to an electronic device is provided, including a flat optical component and a pivot unit, wherein the optical component includes a semitransparent reflective element. The pivot unit is pivotally connected to the optical component and the electronic device. When the optical component is in a first position and substantially parallel to a display surface of the electronic device, the light emitted from the display surface passes through the optical component. When the optical component rotates from the first position to the second position relative to the electronic device with an inclined angle formed between the optical component and the display surface, the light emitted from the display surface is reflected by the semitransparent reflective element to a user.
    Type: Application
    Filed: October 16, 2015
    Publication date: August 11, 2016
    Inventors: Wen-Chung CHIU, Wen-Shu LEE
  • Patent number: 9397528
    Abstract: A shaft linear motor includes an armature portion, a magnetic way and a sealing resin. The armature portion includes a frame, two ribs and a bobbin. The frame is formed with a receiving space therein. The two ribs are disposed on an inner wall of the frame. The ribs are respectively formed with a sectional surface. The bobbin is disposed in the receiving space and formed with an axially penetrated hole. The magnetic way is linearly and movably disposed in the axially penetrated hole. The sealing resin is fully filled in the receiving space for wrapping the inner wall of the frame and the sectional surfaces.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: July 19, 2016
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hong-Cheng Sheu, Chi-Wen Chung, Chi-Shin Chuang, En-Yi Chu
  • Patent number: 9391626
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
  • Publication number: 20160194390
    Abstract: The instant invention relates to low acidic species (AR) compositions comprising a protein, e.g., an antibody, or antigen-binding portion thereof, and methods, e.g., cell culture and/or protein purification methods, for producing such low AR compositions. Methods for using such compositions to treat a disorder, e.g., a disorder in which TNF? is detrimental, are also provided.
    Type: Application
    Filed: January 28, 2016
    Publication date: July 7, 2016
    Applicant: AbbVie, Inc.
    Inventors: Natarajan RAMASUBRAMANYAN, Lihua YANG, Matthew Omon HERIGSTAD, Hong YANG, Kartik SUBRAMANIAN, Xiaobei ZENG, Diane D. DONG, Wen Chung LIM, Kathreen A. GIFFORD, Zehra KAYMAKCALAN, Christopher CHUMSAE
  • Publication number: 20160175493
    Abstract: Methods of fabricating a bioresorbable polymer scaffold are disclosed including a step of inducing crystallization in a bioresorbable polymer construct through exposure to a liquid penetrant.
    Type: Application
    Filed: November 3, 2015
    Publication date: June 23, 2016
    Inventors: Mikael Trollsas, John Stankus, Michael N. Ngo, Wen Chung Tsai, Thierry Glauser
  • Publication number: 20160178049
    Abstract: A hollow-type planet speed reducer includes a body. The body includes at least one driving gear driven by a power input source. The driving gear is connected to a transmission gear, and the transmission gear is connected to a first gear. Based on this, the output rotation speed can be reduced by the incorporation of the driving gear, the transmission gear and the first gear. Besides, a tubular member passes though the body and has an accommodating space to receive wires of the hollow-type planet speed reducer.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: CHE CHIEN CHEN, JUN HUANG LEE, HAN PEI WANG, CHIN HSIUNG TSAI, CHI WEN CHUNG
  • Publication number: 20160170277
    Abstract: In an electrochromic device, upper and lower electrodes are formed respectively on upper and lower substrates, and an electrochromic laminate is sandwiched between upper and lower central regions of the upper and lower electrodes. A looped spacer is disposed between the upper and lower electrodes to surround the electrochromic laminate. A rib member extends from the looped spacer and is fitted in a slot of the upper electrode. An upper electrode contact is disposed between the looped spacer and an upper marginal region of the upper electrode. A lower electrode contact is disposed between the looped spacer and a lower marginal region of the lower electrode.
    Type: Application
    Filed: April 6, 2015
    Publication date: June 16, 2016
    Inventors: Chung-Cheng Lu, Cheng-Hao Liu, Yi-Wen Chung
  • Patent number: 9359434
    Abstract: The instant invention relates to the field of protein production and purification, and in particular to compositions and processes for controlling the amount of acidic species expressed by host cells, as well as to compositions and processes for controlling the amount of acidic species present in purified preparations.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 7, 2016
    Assignee: AbbVie, Inc.
    Inventors: Kartik Subramanian, Xiaobei Zeng, Diane D. Dong, Wen Chung Lim, Kathreen A. Gifford, Christopher Chumsae
  • Publication number: 20160145331
    Abstract: The instant invention relates to the field of protein production and purification, and in particular to compositions and processes for controlling the amount of acidic species expressed by host cells, as well as to compositions and processes for controlling the amount of acidic species present in purified preparations.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Applicant: AbbVie Inc.
    Inventors: Kartik Subramanian, Xiaobei Zeng, Diane D. Dong, Wen Chung Lim, Kathreen A. Gifford, Christopher CHUMSAE
  • Patent number: 9348965
    Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Sheng Chen, Tsun-Yu Yang, Wei-Yi Hu, Tao Wen Chung, Jui-Feng Kuan, Yi-Kan Cheng
  • Patent number: 9335602
    Abstract: A method for control of electrochromic devices is revealed. First a duty cycle of PWM is changed to a preset Q value according to a signal detected by a detector while the electrochromic device is switched to the colored state. The Q value represents electric charge that corresponds to colored-state transmittance. Then turn off the PWM. Thus the response time for coloration and the transmittance of the electrochromic device are maintained within a preset range, without being affected by ambient temperature, setting time and aging of the materials used. Thus the electrochromic device is more convenient to use and having more practical value.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: May 10, 2016
    Assignee: Tintable Kibing Co., Ltd.
    Inventors: Yi-Wen Chung, Chien-He Lai
  • Publication number: 20160127194
    Abstract: A method for setting network models of an electronic device includes setting a default network model list comprising a plurality of default network models for the electronic device and setting a sequence of the plurality of default network models. A specified network model that is used to connect the electronic device to a telecom company is searched from the default network model list according to the sequence. A code of the telecom company is acquired and a country where the telecom company is located is determined according to the acquired code. A network model list corresponding to the determined country is acquired from a database which stores a network model list corresponding to each predetermined country. The default network model list is updated to be the acquired network model list corresponding to the determined country.
    Type: Application
    Filed: April 16, 2015
    Publication date: May 5, 2016
    Inventor: KAI-WEN CHUNG
  • Patent number: 9331185
    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 3, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Huei Huang, Shen-De Wang, Wen-Chung Chang, Feng-Ji Tsai, Chien-Hung Chen
  • Patent number: 9330846
    Abstract: A capacitor structure of capacitive touch panel including a first electrode layer, a first material layer, a second material layer and a second electrode layer is provided. The first material layer is disposed on the first electrode layer, and the material of the first material layer is selected from one of a semiconductor material and an insulating material. The second material layer is disposed on the first material layer, and the material of the second material layer is selected from another one of the semiconductor material and the insulating material. The second electrode layer is disposed on the second material layer.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: May 3, 2016
    Assignee: E Ink Holdings Inc.
    Inventors: Wei-Tsung Chen, Ted-Hong Shinn, Chuang-Chuang Tsai, Wen-Chung Tang, Chih-Hsiang Yang
  • Patent number: 9315574
    Abstract: The instant invention relates to low acidic species (AR) compositions comprising a protein, e.g., an antibody, or antigen-binding portion thereof, and methods, e.g., cell culture and/or protein purification methods, for producing such low AR compositions. Methods for using such compositions to treat a disorder, e.g., a disorder in which TNF? is detrimental, are also provided.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: April 19, 2016
    Assignee: AbbVie, Inc.
    Inventors: Natarajan Ramasubramanyan, Lihua Yang, Matthew Omon Herigstad, Hong Yang, Kartik Subramanian, Xiaobei Zeng, Diane D. Dong, Wen Chung Lim, Kathreen A. Gifford, Zehra Kaymakcalan, Christopher Chumsae
  • Publication number: 20160101544
    Abstract: A method for manufacturing a foam shoe material includes the following steps. (a) A plate prototype is formed, wherein the plate prototype is composed of thermoplastic polyurethane. (b) The plate prototype is foamed by a supercritical fluid to form a foam shoe material including a plurality of microporous structures and an average aperture of the microporous structures is smaller than 100 micrometers.
    Type: Application
    Filed: October 7, 2015
    Publication date: April 14, 2016
    Inventors: Hann-Neng DAY, Sheng-Jung HSIAO, Chih-Chun TSAO, Wen-Chung LIANG, Shihn-Juh LIOU, Chih-Lang WU
  • Publication number: 20160087817
    Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tao Wen CHUNG, Yuwen SWEI, Chih-Chang LIN, Tsung-Ching HUANG