Abstract: A circuit and system enabling testing and development of IC circuits having .mu.-ROM circuits of the equivalent. A test circuit has a plurality of stages, each connected to receive and output a separate signal from the .mu.-ROM, in normal operation. The stages are controlled by a mode signal, in a test mode, to pass signals serially between the stages from a test pin to a scan out pin, as well as to output signals to the separate stage outputs. The test mode is initiated by the coincidence of a synchronization pulse and a given logic level at the test pin.