Abstract: A light emitting diode load board includes a substrate, a first dielectric layer, a second dielectric layer and a first conductive pad and a second conductive pad. The second dielectric layer includes a first structure part, a second structure part and a third structure part. The first dielectric layer is disposed on the substrate. The first structure part is disposed on the first dielectric layer and has a first sidewall. The second structure part is disposed on the first structure part and has a second sidewall. The third structure part is disposed on the second structure part and has N sidewalls. The second sidewall is more prominent than the first sidewall. The first sidewall, the second sidewall and the N sidewalls define the first etched part, and the part of the first dielectric layer is exposed from the first etched part. The first conductive pad is disposed in the first etched part.

Abstract: A light emitting diode load board includes a substrate, a first dielectric layer, a second dielectric layer and a first conductive pad and a second conductive pad. The second dielectric layer includes a first structure part, a second structure part and a third structure part. The first dielectric layer is disposed on the substrate. The first structure part is disposed on the first dielectric layer and has a first sidewall. The second structure part is disposed on the first structure part and has a second sidewall. The third structure part is disposed on the second structure part and has N sidewalls. The second sidewall is more prominent than the first sidewall. The first sidewall, the second sidewall and the N sidewalls define the first etched part, and the part of the first dielectric layer is exposed from the first etched part. The first conductive pad is disposed in the first etched part.

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: The method for depositing a dielectric layer can be used to evenly deposit the dielectric layer to be applied to a semiconductor device.

Abstract: A method of fabricating an integrated circuit device with a substantially uniform inter-layer dielectric layer. The method includes steps of providing a partially completed semiconductor wafer (400) where the partially completed semiconductor device has a first polysilicon layer (401) thereon. The method includes depositing a dielectric layer (405) overlying the polysilicon layer and portions of the partially completed semiconductor device at a pressure of about 1 atmosphere. A step of forming a second polysilicon layer overlying portions of the dielectric layer is also included. The dielectric layer depositing step includes combining an organic silane and an ozone at a concentration of 200 g/m.sup.3 and less.

Abstract: A method of forming field isolation regions (300) on a semiconductor substrate for an integrated circuit. The present method includes forming a sandwich type structure as an oxidation mask (140), (160), and (200). The present sandwich type structure includes an underlying oxide layer (120) formed overlying the top surface. The present sandwich type structure includes a polysilicon layer (140) overlying the oxide layer (120), a first silicon nitride layer (160) overlying the polysilicon layer (140), and a second silicon nitride layer (200) overlying the first silicon nitride layer (160) where the second silicon nitride layer (200) is much thicker than the first layer of silicon nitride (160). The present method also includes patterning the second silicon nitride layer (200), the first silicon nitride layer (160), and the polysilicon layer (140) to define an oxidation mask.

Abstract: A new method of fabricating the NO capacitor dielectric layers of dynamic random access memory (DRAM) cells is disclosed. Because NH.sub.4 Cl particles are soluble (dissolvable) in deionized (DI) water, the undesired NH.sub.4 Cl particles left in the thin nitride surface of the DRAM capacitor dielectric layer can be removed by high-speed spinning the silicon wafers while spraying DI water. At the same time, this high-speed spinning step produces a charge-up effect that can also help the thin nitride layer of the DRAM capacitors eliminate these defects. High quality capacitors are then achieved, and therefore high quality DRAM cells may also be produced using this method.

Abstract: An improved method and resulting structures for producing a layered capacitor structure of memory cell of a DRAM device wherein a doped polysilicon spacer operates as a dopant source for an overlying polysilicon layer on the vertical and sharply inclined surfaces.

Abstract: An improved method and resulting structures for producing a layered capacitor structure of memory cell of a DRAM device wherein a doped polysilicon spacer operates as a dopant source for an overlying polysilicon layer on the vertical and sharply inclined surfaces.

Abstract: A method of forming a self-aligned metal oxide semiconductor (MOS) structure is described. Multilayer dielectrics are used at the edge of the gate electrode, and the gate electrode, the source and the drain have metal silicide regions. The first layer of dielectric is used to define a lightly doped drain (LDD) structure and the second dielectric layer serves to extend the oxide region at the gate edge and to improve the source/drain junction leakage property and to reduce the shorting percentage of gate to source/drain. A special device structure with extended lateral diffusion of junction under the oxide at the gate edge will be performed by using this method.

Abstract: A process for producing a random access memory cell having an improved capacitor structure that thereby permits greater integration. The capacitor is a merged combination of a stacked trench and a stacked capacitor which has at least two plates separated by a dielectric layer. The plates are formed of polysilicon and extend partially over the gate region, over the source region, over the sidewalls and bottom of a trench, and partially over the field oxide.

Abstract: An improved method for manufacturing high density CMOS integrated circuits which minimizes counterdoping of the N and P well structures includes providing a composite masking layer which has layers of silicon oxide, polycrystalline silicon and silicon nitride over a silicon monocrystalline substrate. A mask layer pattern is formed from the composite masking layer by lithography and anisotropic etching which removes the silicon nitride and the portion of the thickness of the polycrystalline silicon over areas designated to be the N well structure. The mask layer pattern is subjected to isotropic etching of the polycrystalline silicon to remove the remaining exposed thickness of polycrystalline silicon and to undercut etch the polycrystalline silicon under the silicon nitride portion of the mask layer pattern. The N well structure is ion implanted and formed by using the silicon nitride layer portion of the mask layer pattern as the mask.