Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

Abstract: A transistor structure including a substrate, a gate dielectric layer, a gate, a first doped region, a second doped region, a first drift region, and a dummy gate is provided. The gate dielectric layer is located on the substrate. The gate dielectric layer includes first and second portions. The second portion is connected to the first portion. The thickness of the second portion is greater than the thickness of the first portion. The gate is located on the first and second portions. The first doped region and the second doped region are located in the substrate on two sides of the gate dielectric layer. The first drift region is located in the substrate on one side of the gate. The second doped region is located in the first drift region. The dummy gate is located on the second portion between the gate and the second doped region.

Abstract: A semiconductor structure includes a substrate comprising a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region, wherein the first conductive type and the second conductive type are complementary. An isolation structure is formed in the substrate to define a plurality of first dummy diffusions and second dummy diffusions and at least a first active region in the first well region, wherein the first dummy diffusions are adjacent to the junction, the first dummy diffusions are between the second dummy diffusions and the first active region, and wherein the second dummy diffusions respectively comprise a metal silicide portion. A plurality of first dummy gates are disposed on the first dummy diffusions and completely cover the first dummy diffusions, respectively.

Abstract: The invention provides a semiconductor structure, which comprises a first silicon substrate with a display region and a driving region defined thereon, a circuit layer located on the first silicon substrate, a plurality of light emitting elements located on the display region of the first silicon substrate, a driving chip located on the driving region of the first silicon substrate and electrically connected with the circuit layer, and a second silicon substrate located on the driving chip.

Abstract: An extended drain metal oxide semiconductor transistor includes a substrate. A gate is disposed on the substrate. A source doped region is disposed in the substrate at one side of the gate. A drain doped region is disposed in the substrate at another side of the gate. A thin gate dielectric layer is disposed under the gate. A thick gate dielectric layer is disposed under the gate. The thick gate dielectric layer extends from the bottom of the gate to contact the drain doped region. A second conductive type first well is disposed in the substrate and surrounds the source doped region and the drain doped region. A deep well is disposed within the substrate and surrounds the second conductive type first well.

Abstract: A semiconductor structure comprises a substrate having a first well region of a first conductive type, a second well region of a second conductive type, and a junction between the first well region and the second well region. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures and second dummy structures and at least a first active region are defined in the first well region by an isolation structure. The first dummy structures are adjacent to the junction and respectively comprise a first metal silicide region and a first doped region of the first conductive type and between the first metal silicide region and the first well region. The first dummy structures are between the second dummy structures and the junction. The second dummy structures respectively comprise a second metal silicide region that direct contacts the first well region.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a first well region of a first conductive type and a second well region of a second conductive type disposed in the substrate. The first conductive type and the second conductive type are complementary. A plurality of first dummy structures are disposed in the first well region and arranged along a junction between the first well region and the second well region. The first dummy structures respectively include a first conductive region and a first doped region disposed between the first conductive region and the first doped region.

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.