Abstract: The invention relates to a microdisplay system that utilizes a small high resolution active matrix liquid crystal display with an illumination system and a magnifying optical system to provide a display for a portable communication device. A handset for the communication system incorporates the display for use as, for example, a wireless telephone or paging device. The small display can provide a high resolution color image at low power thus providing for portable battery powered operation.

Abstract: The invention relates to a microdisplay system that utilizes a small high resolution active matrix liquid crystal display with an illumination system and a magnifying optical system to provide a hand held communication display device. The system has an alternating common voltage which allows reduced power consumption. In addition an internal heating system in the display allows the system to be used at low temperatures. The system can employ an LED illumination system and cellular communication or processor circuits within a compact housing to provide communication devices such as pagers, telephones, televisions, and hand held computer or card reader devices with a compact high resolution data and/or video display.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the circuit devices.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.CC power bus and the other node directly V.sub.SS power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: An active matrix display panel is operated by a color sequential system to form color images. A color generator is disposed between a light source and the display panel for sequentially providing red, green and blue light. A color sequential drive circuit controls the color generator and the pixels of the display panel. The color generator is preferably a multi-stage multiple wavelength blocking filter incorporating fast switching surface stabilized liquid crystal cells.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: A color active matrix display system allows random access of pixel electrodes. The control electronics is fabricated with the active matrix circuitry using single crystal silicon technology. The control electronics includes a random access data scanner and random access spec scanners. By selectively actuating pixel electrodes in the active matrix display region, compressed video information can be directly displayed on the active matrix display panel. Color stripes are used to generate sequential color systems to produce a color image from the active matrix display panel.

Abstract: A color active matrix display system allows random access of pixel electrodes. The control electronics is fabricated with the active matrix circuitry using single crystal silicon technology. The control electronics includes a random access data scanner and random access spec scanners. By selectively actuating pixel electrodes in the active matrix display region, compressed video information can be directly displayed on the active matrix display panel. Color stripes are used to generate sequential color systems to produce a color image from the active matrix display panel.

Abstract: In a ferroelectric memory cell having a plate line, a word line and a bit line coupled to a sense amplifier, a sensing method includes the steps of precharging the bit line to a logic one voltage, setting the word and plate lines to an initial logic zero voltage, stepping the word line from the initial logic zero voltage to the logic one voltage, stepping the plate line from the initial logic zero voltage to the logic one voltage, activating the sense amplifier to resolve voltage developed on the bit line to a full logic voltage while the word and plate lines are at the logic one voltage, and returning the word and plate lines to the initial logic zero voltage.

Abstract: A ferroelectric memory includes a bit line for developing a signal coupled to a ferroelectric memory cell. An integrated load capacitor and sense amplifier are also coupled to the bit line. An isolation circuit is included for selectively electrically isolating the bit line load capacitor from the sense amplifier and ferroelectric memory cell during the active operation of the sense amplifier. The isolation circuit is compatible with both non-volatile ferroelectric and volatile dynamic memory operation.

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: An N-channel output stage having low substrate current injection during a standby mode includes a first transistor having a drain coupled to a source of supply voltage and a second transistor having a drain coupled to the source of the first transistor and a source for driving a load in a normal operating mode. A pair of multiplexers are respectively coupled to the gate of the first and second transistors. The multiplexers turn on the first transistor and couple an input signal to the gate of the second transistor in the normal operating mode, and couple a predetermined bias voltage to the gate of the first transistor and turn off the second transistor in a standby mode. The value of the bias voltage is selected to be approximately equal to VTOTAL/2+VT, wherein VTOTAL is equal to the total voltage across the output stage in the standby mode and VT is an N-channel threshold voltage.

Abstract: Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: A ring oscillator for use with a charge pump includes an odd number of inverter stages each having a primary input, a secondary input, and an output. Both inputs are switched to the same logic state to invert the logic signal at the output of the inverter stage. No crossing-current flows within the inverter stage if the inputs have different logic states. The output of each inverter stage is coupled to the primary input of a following inverter stage in a serially-connected ring fashion. The output of a last inverter stage is coupled to the primary input of a first inverter stage and forms an oscillating signal output, which is coupled to the charge pump. The secondary input of each stage is coupled to the output of a preceding inverter stage. The preceding inverter precedes the current inverter by an odd integer greater or equal to three. The ring oscillator includes a transistor coupled to the output of each inverter stage for impressing a initial pattern of alternating logic levels to begin the oscillation.

Abstract: A multi-level potential generating circuit that brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential.The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: An improved CMOS voltage level translator circuit having an interface stage, an intermediate stage and an output stage is presented. The inventive circuit is characterized by low crossover current in the output and intermediate stages while maintaining minimal delay response when translating a lower potential signal into a higher potential signal. The improved translator circuit may be used in applications such as during EEPROM programming where control signals with normal voltage TTL voltage swing of V.sub.CC and V.sub.SS need to interface with the EEPROM row decoders which require a much higher voltage swing of V.sub.CC ' (>V hd CC) and V.sub.SS.

Abstract: Voltage sensing brings a sense node to three potentials by first grounding the node to a first potential equal to a reference potential and then floating the node to a substantially stabilized second potential equal to the reference potential plus a threshold voltage of an electrical device through which leakage current is pumped. The second potential is then decreased to a third potential greater than or equal to the first potential. The voltage sensing herein described typically is utilized in order to bias digit lines in a dynamic random access memory (DRAM) device during the active portion of the DRAM cycle and during an initiation of the precharge portion of the DRAM cycle. The second potential reduces the current leakage of the memory cell without utilizing an electrical device having a high threshold voltage.

Abstract: An output driver circuit includes first and second translator circuits and a boosted voltage generator. The output driver circuit is suitable for driving the first and second inputs of a reduced voltage N-channel output stage. The first and second translator circuits each have a power terminal and an input for receiving first and second logic input signals. A boost voltage generator having a boosted voltage output is respectively coupled to the power terminals of the first and second translator circuits. The first translator circuit has an output coupled to the first input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The second translator circuit has an output coupled to the second input of the N-channel output stage for providing a boosted logic output signal in a logic high polarity state. The outputs of the first and second translator circuits are complementary for driving the N-channel output stage to provide a valid output logic signal.

Abstract: A high efficiency charge pump includes first and second charging transistors for delivering current to a substrate or well and first and second capacitors respectively coupled to the first and second charging transistors. A control circuit coupled to the first and second charging transistors discharges the first capacitor through the first charging transistor and precharges the second capacitor during a first half-cycle of a ring oscillator output signal. The control circuit discharges the second capacitor through the second charging transistor and precharges the first capacitor during a second half-cycle of the ring oscillator output signal. The control circuit also includes first and second symmetrical halves respectively coupled to third and fourth capacitors. The first, second, third, and fourth capacitors are energized by a four-phase clock signal.