Patents by Inventor Wen-Fu Yu

Wen-Fu Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12256573
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: March 18, 2025
    Assignee: TONG HSING ELECTRONIC INDUSTRIES, LTD.
    Inventors: Chia-Shuai Chang, Chien-Hung Lin, Wen-Fu Yu, Wei-Li Wang, Bae-Yinn Hwang, Jyun-Huei Jiang
  • Publication number: 20250040275
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a ring-shaped supporting layer disposed on the sensor chip, and a light-permeable layer disposed on the ring-shaped supporting layer. The ring-shaped supporting layer has an inner surrounding surface and an outer surrounding surface that is opposite to the inner surrounding surface. At least one of the inner surrounding surface and the outer surrounding surface has a plurality of round-ended microstructures that are sequentially connected to each other and that surround a sensing region of the sensor chip. An end of each of the round-ended microstructures is a round-ended portion having a radius of less than 1 ?m. The light-permeable layer, the inner surrounding surface of the ring-shaped supporting layer, and the sensor chip jointly define an enclosed space.
    Type: Application
    Filed: September 29, 2023
    Publication date: January 30, 2025
    Inventors: CHIEN-HUNG LIN, JYUN-HUEI JIANG, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG
  • Publication number: 20240337779
    Abstract: An optical device includes an electronic component, a light-permeable layer, and a ring-shaped adhesive layer that is sandwiched between the electronic component and the light-permeable layer. The ring-shaped adhesive layer surrounds an optical region of the electronic component and includes a plurality of light-weakening slots that are formed on an inner side surface thereof. The light-weakening slots are in a ring-shaped arrangement and surround the optical region. Each of the light-weakening slots has a slot opening having a slot width and a slot bottom spaced apart from the slot opening by a slot depth. A width of each of the light-weakening slots gradually decreases along a direction from the slot opening to the slot bottom, and a ratio of the slot width to the slot depth is within a range from 1:0.86 to 1:11.4, such that each of the light-weakening slots is configured to weaken light irradiated thereon.
    Type: Application
    Filed: November 20, 2023
    Publication date: October 10, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG
  • Publication number: 20240290897
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a plurality of adhesive rings disposed on the sensor chip, a plurality of filtering lenses respectively adhered to the adhesive rings, and an encapsulant that surrounds the above components. A sensing region of the sensor chip has a layout boundary and a plurality of sub-regions that are defined by the layout boundary and that are separate from each other. The adhesive rings are disposed on the sensing region, and each of the adhesive rings surrounds one of the sub-regions. Each of the filtering lenses, a corresponding one of the adhesive rings, and a corresponding one of the sub-regions jointly define a buffering space. The encapsulant is formed on the substrate and covers the layout boundary of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: August 29, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEN-FU YU, WEI-LI WANG, BAE-YINN HWANG, JYUN-HUEI JIANG
  • Publication number: 20240204019
    Abstract: An optical package structure includes a light transmittable member, a bonding structural member, and an optical element. The bonding structural member includes a first bonding layer and a second bonding layer to form a light-scattering structure. The first bonding layer is connected to a bonding surface of the light transmittable member. An inner side of the first bonding layer includes a plurality of first protruded portions. An inner side of the second bonding layer includes a plurality of second protruded portions. The second protruded portions and the first protruded portions are arranged in a staggered manner. The bonding structural member includes the first bonding layer or the light-absorption member. The light-absorption member is filled in concaved portions of the first bonding layer. The optical element is connected to the bonding structural member, and is spaced apart from the light transmittable member.
    Type: Application
    Filed: September 3, 2023
    Publication date: June 20, 2024
    Inventors: CHIEN-HUNG LIN, BAE-YINN HWANG, WEN-FU YU, WEI-LI WANG
  • Publication number: 20240204020
    Abstract: An optical package structure and a method for manufacturing the same are provided. The optical package structure includes an optical element, a bonding structural member, and a light transmittable member. The bonding structural member is bonded to a surface of the optical element. The bonding structural member includes a first bonding layer, a light-absorption layer, and a second bonding layer. The first bonding layer and the second bonding layer are made of an opaque material. The light-absorption layer is disposed between the first bonding layer and the second bonding layer. The light transmittable member is bonded to the bonding structural member and spaced apart from the optical element. The light-absorption layer is configured to absorb light emitted to the bonding structural member.
    Type: Application
    Filed: September 25, 2023
    Publication date: June 20, 2024
    Inventors: CHIEN-HUNG LIN, BAE-YINN HWANG, WEN-FU YU, WEI-LI WANG
  • Publication number: 20240128233
    Abstract: A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, WEN-FU YU, BAE-YINN HWANG, WEI-LI WANG, CHIEN-HUNG LIN
  • Publication number: 20240128291
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on and electrically coupled to the substrate, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer has two adhering surfaces having a same area and a middle cross section located at a middle position between the two adhering surfaces. An area of the middle cross section is 115% to 200% of an area of any one of the two adhering surfaces. The adhesive layer can provide for light to travel therethrough, and enables the light therein to change direction and to attenuate. The sensor chip, the adhesive layer, and the light-permeable layer are embedded in the encapsulant, and an outer surface of the light-permeable layer is at least partially exposed from the encapsulant.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: CHIA-SHUAI CHANG, CHIEN-HUNG LIN, WEI-LI WANG, WEN-FU YU, BAE-YINN HWANG
  • Publication number: 20240128139
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate along a predetermined direction for being electrically coupled to each other, a light-permeable layer, an adhesive layer having a ring-shape and sandwiched between the sensor chip and the light-permeable layer, and an encapsulant formed on the substrate. The adhesive layer is formed with at least one type of a buffering cavity, wave-shaped slots, and rectangular slots, which penetrate therethrough along the predetermined direction. The buffering cavity can be located in the adhesive layer, and any one type of the wave-shaped slots and the rectangular slots can be respectively recessed in an inner side and an outer side of the adhesive layer. A minimum width of the adhesive layer is greater than or equal to 50% of a predetermined width between the inner side and the outer side.
    Type: Application
    Filed: June 6, 2023
    Publication date: April 18, 2024
    Inventors: WEI-LI WANG, JYUN-HUEI JIANG, WEN-FU YU, BAE-YINN HWANG, CHIEN-HUNG LIN
  • Patent number: 7544621
    Abstract: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: June 9, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu
  • Publication number: 20080286976
    Abstract: A method of removing a metal suicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Application
    Filed: June 13, 2008
    Publication date: November 20, 2008
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu
  • Publication number: 20070099423
    Abstract: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Application
    Filed: November 1, 2005
    Publication date: May 3, 2007
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu