Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).

Abstract: An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.

Abstract: An integrated circuit and method for establishing scan test architecture in the integrated circuit is provided. The integrated circuit includes a plurality of circuit modules. Each circuit module includes a clock control unit, a first pipeline unit, a serialized compressed scan circuit and a second pipeline unit. The clock control unit generates a scan clock according to a test clock. The first pipeline unit converts a test input signal into first data according to the scan clock. The serialized compressed scan circuit generates second data according to the first data and the test clock. The second pipeline unit converts the second data into a test output signal according to the scan clock. The scan clock of each of the circuit modules is independent from the scan clocks of the other circuit modules, thereby reducing the difficulty and cost of timing analysis and adjustment.

Abstract: A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

Abstract: A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.