Patents by Inventor Wen-Hsi Lee

Wen-Hsi Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240090190
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 11844205
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
  • Patent number: 11810720
    Abstract: A method is provided for fabricating a terminal electrode. The terminal electrode is applied on a multilayer ceramic capacitor (MLCC). The method prints inner electrodes on full area together with protective layers. The MLCC uses the thickness of thinned dielectric ceramic layers and the stacking of nickel inner-electrode layers. High capacitance is achieved at ends and sides with high electrode-to-ceramic ratios. Thus, the present invention uses a coating technology of ultra-low-temperature electrochemical deposition to fabricate low internal-stress MLCC terminal electrodes together with insulating protective layers for improving MLCC yield while cost reduced.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: November 7, 2023
    Assignee: National Cheng Kung University
    Inventor: Wen-Hsi Lee
  • Publication number: 20230284428
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.
    Type: Application
    Filed: February 21, 2023
    Publication date: September 7, 2023
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20230154985
    Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.
    Type: Application
    Filed: January 13, 2022
    Publication date: May 18, 2023
    Inventors: TE-MING KUNG, YING-LANG WANG, KEI-WEI CHEN, WEN-HSI LEE, SHU WEI CHANG
  • Patent number: 11587937
    Abstract: A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut fl
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-Yu Hung
  • Publication number: 20220406529
    Abstract: A method is provided for fabricating a terminal electrode. The terminal electrode is applied on a multilayer ceramic capacitor (MLCC). The method prints inner electrodes on full area together with protective layers. The MLCC uses the thickness of thinned dielectric ceramic layers and the stacking of nickel inner-electrode layers. High capacitance is achieved at ends and sides with high electrode-to-ceramic ratios. Thus, the present invention uses a coating technology of ultra-low-temperature electrochemical deposition to fabricate low internal-stress MLCC terminal electrodes together with insulating protective layers for improving MLCC yield while cost reduced.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 22, 2022
    Inventor: Wen-Hsi Lee
  • Publication number: 20210305261
    Abstract: A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut fl
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 11037935
    Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
  • Patent number: 10840330
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20190392968
    Abstract: A thick-film aluminum (Al) electrode paste is provided to fabricate a chip resistor. The paste is a mixture of a vanadium-zinc-boron series glass (V2O5—ZnO—B2O3 or BaO—ZnO—B2O3) along with a metal oxide, aluminum granules, and an organic additive, whose proportions are separately 3˜30 wt %, 0.1˜15 wt %, 50˜70 wt %, and 10˜20 wt %. After being stirred through three rollers and filtered, the paste is pasted on an alumina ceramic substrate. The pasted substrate is dried and sintered for forming a thick-film aluminum electrode. Meanwhile, before processing metal plating that follows, an anti-plating pretreatment is performed. Therein, surface irregularities and nonconductive alumina on the surface are removed. Thus, the electrode obtains smooth flat surface and low oxygen content. The characteristics of the chip resistor using the thick-film aluminum electrode are equivalent to those using thick-film printed silver electrodes and those using thick-film printed copper electrodes sintered in a reducing atmosphere.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 26, 2019
    Inventor: Wen-Hsi Lee
  • Publication number: 20190341389
    Abstract: A semiconductor device includes: active regions arranged in a first grid oriented substantially parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented substantially parallel to a second direction, the second direction being substantially orthogonal to the first direction. The first gaps are interspersed correspondingly between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into a corresponding one of the first gaps.
    Type: Application
    Filed: July 15, 2019
    Publication date: November 7, 2019
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 10373962
    Abstract: A semiconductor device includes: active regions arranged in a first grid oriented parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction. The first gaps are interspersed between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into the corresponding gap.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 6, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
  • Publication number: 20190189312
    Abstract: A method is provided for pretreating a thick-film aluminum electrode. The pretreatment is processed before subsequent metal plating. the thick-film aluminum electrode is pretreated with a purely mechanical or chemical treatment or a mixture of mechanical and chemical treatments; the chemical treatment is an alkaline/acid washing or a chemical anodizing; The surface of the thick-film aluminum electrode is made even and alumina, a nonconductive substance, on the surface is removed. The thick-film aluminum electrode has a surface with evenness and low oxygen content. The thick-film aluminum electrode has similar quality as the thick-film electrode of noble metal silver for subsequent metal plating.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 20, 2019
    Inventor: Wen-Hsi Lee
  • Publication number: 20190143405
    Abstract: Methods are provided to fabricate thick-film pastes with low cost by using base metals. The pastes achieve high conductivity and are sintered at low or high temperatures in the air. Therein, an aluminum powder is cladded with copper particles in a thickness of tens of nanometers to several microns for obtaining a copper-clad aluminum paste with high conductivity. The copper particles can be reduced with silver. A nanoscale silver-clad aluminum powder has a sintering temperature down to about 350 celsius degrees. Hence, the PCB electroplating copper electrode can be replaced to expel the expensive yellow-light development. The problem of solution pollution during electroplating is solved. Nevertheless, the expensive metal silver electrode used in screen printing can be replaced. The problem of the expensive required reduction atmosphere in screen printing can be solved as well. Thus, the material cost is significantly reduced for PCB substrates or ceramic substrates.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Inventor: Wen-Hsi Lee
  • Patent number: 10290403
    Abstract: Two methods are provided to make aluminum terminal electrodes for chip resistors. For a chip resistor having a high resistance, the structure is not changed but the aluminum terminal electrode must have a high solid content, including a high aluminum content and a high glass content. For porous-aluminum terminal electrodes applied to a chip resistor having a low resistance, a new structure is formed to change current-conducting paths through different sizes of a protecting layer and a resistor layer. Therein, original paths conducting to the resistor layer through front terminal electrodes are changed into new paths conducting to the resistor layer through side terminal electrodes.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: May 14, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventor: Wen-Hsi Lee
  • Patent number: 10259172
    Abstract: A fabrication method of magnetic device is provided. A magnetic material is provided. A portion of the magnetic material is selectively irradiated by an energy beam, and reactive gas is introduced simultaneously. The magnetic material being irradiated is melted and solidified to form a solidified layer. An outer layer of the solidified layer reacts with the reactive gas to form a barrier layer, so as to form a magnetic unit including the solidified layer and the barrier layer. It is determined whether the manufacturing process of the same layer is finished, if not, the energy beam is moved to the other portion of the magnetic material. The above step is repeated to overlap multiple magnetic units to form a magnetic layer. If yes, the flow returns to the 1st step to provide another magnetic material to the magnetic layer. The above steps are repeated to form a 3D magnetic device.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 16, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Wei-Chin Huang, Chuan-Sheng Chuang, Chih-Hsien Wu, Ching-Chih Lin, Wen-Hsi Lee, Kai-Jyun Jhong
  • Patent number: 10174210
    Abstract: The present invention provides an aluminum (Al) paste. The Al paste has low cost and high conductivity. An Al powder having a wide range of particle size distribution and an increased solid content are used to solve the problem of multiple pores. A rupture mechanism of alumina is fully used for sintering to improve contacting internal liquid Al with each other for forming conductive paths. With coordination of sufficient liquid glass powder, all ruptured surface of the Al powder is coated to inhibit exposed liquid Al from oxidation on contacting air. The problem of low conductivity of Al paste is thus radically solved.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: January 8, 2019
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventor: Wen-Hsi Lee
  • Publication number: 20180342523
    Abstract: A semiconductor device includes: active regions arranged in a first grid oriented parallel to a first direction; and gate electrodes arranged spaced apart in a second grid and overlying corresponding ones of the active regions, the second grid being oriented parallel to a second direction, the second direction being orthogonal to the first direction. The first gaps are interspersed between neighboring ones of the active regions. For a flyover intersection at which a corresponding gate electrode crosses over a corresponding active region and for which the gate electrode is not functionally connected to the corresponding active region, the gate electrode does not extend substantially beyond the corresponding active region and so does not extend substantially into the corresponding gap.
    Type: Application
    Filed: October 10, 2017
    Publication date: November 29, 2018
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20180174720
    Abstract: Two methods are provided to make aluminum terminal electrodes for chip resistors. For a chip resistor having a high resistance, the structure is not changed but the aluminum terminal electrode must have a high solid content, including a high aluminum content and a high glass content. For porous-aluminum terminal electrodes applied to a chip resistor having a low resistance, a new structure is formed to change current-conducting paths through different sizes of a protecting layer and a resistor layer. Therein, original paths conducting to the resistor layer through front terminal electrodes are changed into new paths conducting to the resistor layer through side terminal electrodes.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventor: Wen-Hsi Lee