Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: The present application relates to a system and a method for producing vinyl chloride. The system comprise a preheat unit, a gas-liquid separating unit, a heat-recovery unit, a heating unit and a thermal pyrolysis unit, and therefore heat energy of the thermal pyrolysis product can be efficiently recovered. Energy cost of the system can be efficiently lowered with the heat-recovery unit and the heating unit, and further prolonging operating cycle of the system.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.

Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

Abstract: A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device.

Abstract: A method and apparatus for finding contamination occurrence and for preventing the propagation of the contamination is provided according to the present invention, which altogether constitutes a contamination prevention system. The present invention employs a computer for examining a process flow in order to find out whether a process step is contaminated by using a contaminated tool and therewith to show a proper representation on a process flow. Any process flow that passes the contamination prevention system of the present invention can be free of any contamination problem. Furthermore, The contamination prevention system according to the present invention gives a tag for each object. If an object is tagged “contaminated”, then the system forbids the next process step, that includes uncontaminated tools, to be executed. The present invention can be built to an automatic system to prevent the propagation of contamination from occurring.

Abstract: A testing system is described for testing a memory device. The testing system includes a timing generator, an optional frequency multiplier circuit, a pattern generator, and a waveform shaping circuit. The timing generator generates a first clock signal. The frequency multiplier circuit receives the first clock signal, and uses the first clock signal to produce a second clock signal. In general, the second clock signal has a frequency greater than a frequency of the first clock signal. The frequency of the second clock signal may twice the frequency of the first clock signal. The testing system provides the second clock signal to the memory device such that operations within the memory device are synchronized to the second clock signal. The waveform shaping circuit produces an address signal synchronized to the first clock signal, and provides the address signal to the memory device when reading data from the memory device.

Abstract: A serial I/O testing method is performed by a testing system for testing a memory device having a first pin, a second pin, and a third pin. The testing method includes a step of inputting a clock into the memory device through the first pin, followed by a step of inputting a serial address into the memory device through the second pin synchronized with the clock. The method further includes a step of inputting a command into the memory device and a step of, when the command is a read command, outputting from the third pin a serially-written data synchronized with the clock. When the command is a program command, the method includes inputting an initial data serially through the third pin synchronized with the clock, and programming the initial data into the memory device before outputting it on the third pin as programmed data from the memory device synchronized with the clock.

Abstract: A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.