Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.

Abstract: A method for manufacturing an electronic device is provided, the method includes: providing an inspection module to inspect a first area of the electronic device to obtain a first information and inspect a second area of the electronic device to obtain a second information; transmitting the first information and the second information to a processing system; comparing the first information and the second information to obtain a difference; and transmitting a correction information to a first process machine via a first interface system. When the difference is greater than or equal to -2 and less than or equal to 2, the first process machine is started to produce. An electronic device is also provided.

Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer, a first dielectric layer disposed on the first metal layer, a second metal layer disposed on the first dielectric layer, and a second dielectric layer disposed on the second metal layer. A coefficient of thermal expansion of the first dielectric layer is less than a coefficient of thermal expansion of the second dielectric layer.

Abstract: A redistribution layer structure is provided. The redistribution layer structure includes a first metal layer and a first dielectric layer disposed on the first metal layer. A range of a difference between a coefficient of thermal expansion of the first dielectric layer and a coefficient of thermal expansion of the first metal layer is 0% to 70% of the coefficient of thermal expansion of the first dielectric layer.

Abstract: A manufacturing method of a package structure including the following steps is provided. A carrier is provided. An anti-warpage structure is formed on the carrier. And a redistribution layer is formed on the carrier. In the normal direction of the carrier, a warpage trend of the anti-warpage structure is opposite to a warpage trend of the redistribution layer.

Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.

Abstract: A method of manufacturing a light source carrier with at least one light source, including: providing a substrate with a plurality of light source groups disposed thereon, wherein each light source group includes the at least one light source; irradiating a first light upon one of the light source groups through a first mask; capturing a photoluminescent light emitted by the one of the light source groups to acquire data; comparing the data with a reference to determine whether the one of the light source groups is qualified; providing a carrier; and transferring the one of the light source groups from the substrate to the carrier if the one of the light source groups is qualified.

Abstract: A solution detector is provided, which includes: a substrate; a first light detecting element disposed on the substrate and including a first transistor; and a pH value sensing module disposed on the substrate and including a working electrode and a reference electrode.

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

Abstract: A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a metal layer, wherein the metal layer is formed on a scribe line which is formed between adjacent dies. A cutter is used to cut the metal layer along the scribe line during the cutting procedure to form a plurality of dies on the wafer, and the metal layer cut by the cutter remains a plurality of metal burrs on the dies. A brush is used to contact with the metal burrs along the cutting slot during the contracting procedure to prevent each of the metal burrs from protruding from a surface of each of the dies.

Abstract: A method for projecting wafer product overlay error of the present invention is disclosed, the steps of the method comprises:(a) sample equipment overlay error data, equipment condition data, and actual wafer product overlay error data; (b) establish a neural network, the equipment overlay error data and the equipment condition data are inputs of the neural network, the generated output of the neural network is projected wafer product overlay error data, and the actual wafer product overlay error data is the target output of the neural network; and (c) set a mean square error target, train the neural network continuously until the mean square error of the neural network is no longer bigger than the mean square error target. Additionally a method for projecting wafer product critical dimension is also presented in the present invention.