Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

Abstract: Provided is a method of accurate and sensitive characterization and prognosis of prostate cancer in a subject. The method includes obtaining a biological sample from the subject and determining the level of identified biomarkers.

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

Abstract: The present invention provides a method of treating targeted abnormal cells that are resistant, refractory, insensitive, non-responsive, or inadequately responsive to an ingredient, as well as cytotoxic cells used therein, comprising administering an effective amount of the ingredient-complexed cytotoxic cells to a subject with the disease.

Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.

Abstract: In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, a groove pattern is formed in the hard mask layer, one or more first resist layers are formed over the hard mask layer having the groove pattern, a first photo resist pattern is formed over the one or more first resist layers, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer with the groove pattern are patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

Abstract: A tape measure comprises a housing containing a tape, spring, reel, and hub, with first seal(s) to seal between the reel cartridge and the hub and/or to seal between the reel and the housing and/or a part fixed to the housing. An outermost coil of the spring may extend out of an opening in the reel and be attached to an innermost coil of the tape, and a second seal may be provided on the reel, to seal between the spring and the reel where the spring extends from the reel. Alternatively, the spring may be contained within the reel, and an outermost coil of the spring may be attached to an interior of the reel. An exterior of the reel may include an attachment portion to which an innermost coil of the tape is attached. The housing may be openable to enable contaminants to be removed from the housing.

Abstract: Aspects of the present disclosure include polymeric structures (e.g., microneedles) having a lattice microstructure composed of one or more lattice cell units. Polymeric structures according to certain embodiments have repeating lattice cell units that are formed by high resolution continuous liquid interface production. Aspects also include systems for making polymeric structures having a lattice microstructure. Systems according to certain embodiments include a micro-digital light projection system having a light beam generator component and a light projection monitoring component and a liquid interface polymerization module having a build elevator and a build surface configured for generating the polymeric lattice microstructure from a polymerizable composition positioned therebetween. Methods for making polymeric structures having a lattice microstructure with the subject systems are also provided.

Abstract: An immersion cooling system includes a cooling tank, a busbar and two busbar protection modules. The busbar is disposed in the cooling tank. The two busbar protection modules are disposed at opposite sides of the busbar. Each of the two busbar protection modules includes a base, a driving member and a cover. The driving member is pivotally connected to the base. The cover is pivotally connected to the driving member. Two covers of the two busbar protection modules extend toward each other to cover the busbar. When two driving members of the two busbar protection modules are pushed, the two driving members rotate to drive the two covers to move away from each other, such that the busbar is exposed between the two covers.

Abstract: The application discloses a mobile communication device and method. The mobile communication method includes: when a collision between third party communication by a third party module and Wi-Fi communication by a Wi-Fi module is detected, determining a next Wi-Fi receiving gain; and adjusting a Wi-Fi receiving gain based on the calculated next Wi-Fi receiving gain to concurrently receive Wi-Fi signals and third party signals.

Abstract: A method includes providing a workpiece having a first conductive pad and a second conductive pad over a substrate, a topmost point of the second conductive pad is above that of the first conductive pad by a height difference, conformally forming a first etch stop layer on the first and the second conductive pads, forming a dielectric structure over the first etch stop layer, performing a planarization process to the dielectric structure, and after the performing of the planarization process, conformally depositing a dielectric layer over the workpiece, the dielectric layer including a first portion disposed directly over the first conductive pad and a second portion disposed directly over the second conductive pad, where a thickness difference between a thickness of the first portion of the dielectric layer and a thickness of the second portion of the dielectric layer is less than the height difference.

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

Abstract: A manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.

Abstract: The present disclosure provides uses of with PD-L1 antibody-IL-10 fusion protein in the treatment of cancer and chronic virus infection diseases and the prevention of cancer recurrence via promoting T cell memory response.

Abstract: An electronic device includes a base, a multi-stage sensor, a top cover, and a side cover. The multi-stage sensor is configured to sense a sensed area. The top cover includes a top-sensed element, and the top cover is detachably connected to a top side of the base, so that the top-sensed element can be selectively in or not in the sensed area. The side cover includes a side-sensed element, and the side cover is detachably adjacent to a front side of the base, so that the side-sensed element can be selectively in or not in the sensed area. In response to that only the top-sensed element is in the sensed area, the multi-stage sensor outputs a first signal. In response to that neither the top-sensed element nor the side-sensed element is in the sensed area, the multi-stage sensor outputs a second signal.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.