Patents by Inventor Wen-Hsien Chuang

Wen-Hsien Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006659
    Abstract: Methods for reducing warpage and increasing the effectiveness of hybrid bond void testing are disclosed. A semiconductor package has a first side and a second side, with a dummy bond pad located on the second side, and at least one metal-containing layer between the first side and the second side (for example a redistribution layer). A warpage control structure is provided in the semiconductor package that extends from the first side into the semiconductor package, and is aligned with the dummy bond pad. The warpage control structure is made of a low-density filling. This relieves stress that causes/increases warpage. When a hybrid bond is formed between the semiconductor package and another semiconductor package, the warpage control structure maximizes acoustic wave penetration for testing the quality of the hybrid bond at the dummy bond pad.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 2, 2025
    Inventors: Ji-Feng Ying, Xuewen Tang, Wen-Hsien Chuang, Jyun-Lin Wu, Chia Wei Chang
  • Publication number: 20230317408
    Abstract: Pulsed beam prober systems, devices, and techniques are described herein related to providing a beam detection frequency that is less than a electrical test frequency. An electrical test signal at the electrical test frequency is provided to die under test. A pulsed beam is applied to the die such that the pulsed beam has packets of beam pulses or a frequency delta with respect to the electrical test frequency. The packets of beam pulses or the frequency delta elicits a detectable beam modulation in an imaging signal reflected from the die such that the imaging signal is modulated at a detection frequency less than the electrical test frequency.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Applicant: Intel Corporation
    Inventors: Xianghong Tong, Martin Von Haartman, Wen-Hsien Chuang, Zhiyong Ma, Hyuk Ju Ryu, Prasoon Joshi, May Ling Oh, Jennifer Huening, Shuai Zhao, Charles Peterson, Ira Jewell, Hasan Faraby
  • Publication number: 20230305057
    Abstract: Wafer level electron beam prober systems, devices, and techniques, are described herein related to providing wafer level testing for fabricated device structures. Such wafer level testing contacts a first side of a die of a wafer with a probe to provide test signals to the die under test and performs e-beam imaging of the first side of the die while the test signals are provided to the die under test.
    Type: Application
    Filed: March 22, 2022
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Xianghong Tong, Martin Von Haartman, Zhiyong Ma, Jennifer J. Huening, Hyuk Ju Ryu, Christopher Morgan, Shuai Zhao, Ramune Nagisetty, Tuyen K. Tran, Wen-Hsien Chuang
  • Patent number: 8779959
    Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 15, 2014
    Assignees: Global Unichip Corp., Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Wen-Hsien Chuang, Hsiang-Wei Liu, Jen-Wei Tsai, Ting-Hao Wang
  • Publication number: 20140176355
    Abstract: A method to reduce the integral non-linearity (INL) of a digital-to-analog converter (DAC) and a DAC implementing said method are disclosed. The method in this invention is a pseudo dynamic element matching (PDEM) method. Compared with a prior art, the method of this invention provides a better performance in glitch. Compared with another prior art, the method of this invention also guarantees that DEM will not fail even if the input digital code remains constant.
    Type: Application
    Filed: May 31, 2013
    Publication date: June 26, 2014
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., GLOBAL UNICHIP CORP.
    Inventors: Wen-Hsien Chuang, Hsiang-Wei Liu, Jen-Wei Tsai, Ting-Hao Wang
  • Publication number: 20120249115
    Abstract: A bandgap reference circuit includes a modulator, an amplifier, a demodulator, a closed feedback loop and an output circuit. The modulator is utilized for modulating an input signal to generate a modulated input signal. The amplifier is utilized for amplifying the modulated input signal to generate an amplified modulated input signal. The demodulator is utilized for demodulating the amplified modulated input signal to generate a demodulated signal. The closed feedback loop is coupled between an output terminal of the demodulator and an input terminal of the modulator. The output circuit is utilized for generating an output current according to the demodulated signal, where the output current is a constant current insensitive to fluctuations in temperature.
    Type: Application
    Filed: July 27, 2011
    Publication date: October 4, 2012
    Inventors: Wen-Hsien Chuang, Ting-Hao Wang, Yu-Tsung Lu
  • Patent number: 7394178
    Abstract: A generator rotor structure comprises a cylinder body, at least a magnetic member, and a shaft. A penetrating bore is adapted at the center of the cylinder body. A plurality of containing spaces is adapted between the sidewall of the penetrating bore and the outer sidewall of the cylinder body. The adjacent containing spaces include a connecting part. The shaft passes through the penetrating bore, and the magnetic member is adapted on the outer sidewall of the cylinder body. The present invention can also be implemented according to another embodiment of the present invention, which comprises a hollow body, at least a connecting part, at least a shaft sleeve, at least a magnetic member, and a shaft. The connecting part is connected on the inner sidewall of the hollow body, and the shaft sleeve is connected to the connecting part. In addition, the shaft passes through the shaft sleeve, and the magnetic member is adapted on the outer sidewall of the hollow body.
    Type: Grant
    Filed: January 29, 2007
    Date of Patent: July 1, 2008
    Assignee: Atomic Energy Council-Institute of Nuclear Energy Research
    Inventors: Tao-Pang Hsiung, Wen-Hsien Chuang
  • Patent number: 6225672
    Abstract: The present invention relates to the structure and fabrication process of a high-gain monocrystal Silicon Carbide phototransistor applicable at high temperature. In view of the optical gain and applicable temperature of the conventional n-p-n type Silicon Carbide phototransistor are too low for practical usage, the present invention utilizes a newly developed n-i-p-i-n structure to strengthen the intrinsic properties of the element, in order to enhance optical gain of the phototransistor for being able to operate at high temperature steadily.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: May 1, 2001
    Assignee: National Science Council of Republic of China
    Inventors: Yean-Kuen Fang, Kuen-Hsien Wu, Wen-Hsien Chuang