Patents by Inventor Wen-Hsin CHAN

Wen-Hsin CHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848367
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a dummy gate to form a gate trench to expose a channel portion of a first fin and a first isolation structure; depositing a gate dielectric layer and first and second work function layers, wherein the second work function layer has a first portion directly over the channel portion of the first fin and a second portion directly over the first isolation structure; etching the second portion of the second work function layer, wherein the first portion of the second work function layer remains; depositing a third work function layer over and in contact with the first portion of the second work function layer and the first work function layer; and filling the gate trench with a gate metal.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Wen Hsieh, Wen-Hsin Chan
  • Publication number: 20230154922
    Abstract: A structure includes a bulk semiconductor substrate, a first plurality of dielectric isolation regions over the bulk semiconductor substrate, a plurality of semiconductor fins protruding higher than the first plurality of dielectric isolation regions, a first gate stack on top surfaces and sidewalls of the plurality of semiconductor fins, a second plurality of dielectric isolation regions over the bulk semiconductor substrate, a mesa structure in the second plurality of dielectric isolation regions, and a second gate stack over the mesa structure. Top surfaces of the first gate stack and the second gate stack are coplanar with each other.
    Type: Application
    Filed: March 17, 2022
    Publication date: May 18, 2023
    Inventors: Sung-Hsin Yang, Ru-Shang Hsiao, Ching-Hwanq Su, Chen-Bin Lin, Wen-Hsin Chan
  • Publication number: 20210280681
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a dummy gate to form a gate trench to expose a channel portion of a first fin and a first isolation structure; depositing a gate dielectric layer and first and second work function layers, wherein the second work function layer has a first portion directly over the channel portion of the first fin and a second portion directly over the first isolation structure; etching the second portion of the second work function layer, wherein the first portion of the second work function layer remains; depositing a third work function layer over and in contact with the first portion of the second work function layer and the first work function layer; and filling the gate trench with a gate metal.
    Type: Application
    Filed: May 21, 2021
    Publication date: September 9, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Wen HSIEH, Wen-Hsin CHAN
  • Patent number: 11081571
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 11018234
    Abstract: A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate includes a first semiconductor fin and a second semiconductor fin. The gate structure includes a work function metal structure crossing over the first semiconductor fin and the second semiconductor fin. The work function metal structure comprises a first portion over a portion of the first semiconductor fin, a second portion over a portion of the second semiconductor fin, and a third portion connecting the first portion to the second portion, wherein a thickness of the third portion is smaller than a thickness of the second portion and greater than a thickness of the first portion along an extension direction of the second semiconductor fin.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Wen Hsieh, Wen-Hsin Chan
  • Patent number: 10867852
    Abstract: Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ruei Yeh, Wen-Hsin Chan, Kang-Min Kuo
  • Publication number: 20200343360
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure, and forming a mask layer covering the dummy fin structure. The method also includes removing a portion of the mask layer and a top portion of the dummy fin structure by a first etching operation to form an etched mask layer, wherein the dummy fin structure has a protruding portion protruding from a top surface of the etched mask layer after the first etching operation.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung CHEN, Kang-Min KUO, Wen-Hsin CHAN
  • Patent number: 10727321
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Publication number: 20200066873
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dummy fin structure over a semiconductor substrate, and forming a mask layer covering the dummy fin structure. The method further includes irradiating the mask layer, so that the mask layer is divided into an unirradiated portion and an irradiated portion, and the irradiated portion is over the dummy fin structure. The method also includes removing a top portion of the irradiated portion and a top portion of the dummy fin structure by a first etching operation, such that the dummy fin structure has a convex top surface after the first etching operation. The method includes removing a middle portion of the dummy fin structure by a second etching operation, such that the dummy fin structure has a concave top surface after the second etching operation.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung CHEN, Kang-Min KUO, Wen-Hsin CHAN
  • Publication number: 20200035799
    Abstract: A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate includes a first semiconductor fin and a second semiconductor fin. The gate structure includes a work function metal structure crossing over the first semiconductor fin and the second semiconductor fin. The work function metal structure comprises a first portion over a portion of the first semiconductor fin, a second portion over a portion of the second semiconductor fin, and a third portion connecting the first portion to the second portion, wherein a thickness of the third portion is smaller than a thickness of the second portion and greater than a thickness of the first portion along an extension direction of the second semiconductor fin.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Bo-Wen HSIEH, Wen-Hsin CHAN
  • Patent number: 10505023
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate, and forming a mask layer covering the first fin structure and the second fin structure. The method also includes performing a first etching operation using the second fin structure as an etch stop layer to partially remove the mask layer such that the etch stop layer protrudes from the mask layer after the first etching operation. The method further includes partially removing the second fin structure using a second etching operation after the first etching operation.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Publication number: 20190109206
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first fin structure and a second fin structure over a semiconductor substrate, and forming a mask layer covering the first fin structure and the second fin structure. The method also includes performing a first etching operation using the second fin structure as an etch stop layer to partially remove the mask layer such that the etch stop layer protrudes from the mask layer after the first etching operation. The method further includes partially removing the second fin structure using a second etching operation after the first etching operation.
    Type: Application
    Filed: December 3, 2018
    Publication date: April 11, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung CHEN, Kang-Min KUO, Wen-Hsin CHAN
  • Patent number: 10147805
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 10008568
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a gate stack over a semiconductor substrate. The semiconductor device structure also includes a source/drain structure over the semiconductor substrate, and the source/drain structure includes a dopant. The semiconductor device structure further includes a channel region under the gate stack. In addition, the semiconductor device structure includes a semiconductor layer surrounding the source/drain structure. The semiconductor layer is configured to prevent the dopant from entering the channel region.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 9991123
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFATURING CO., LTD.
    Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
  • Publication number: 20170236716
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mei-Chun CHEN, Ching-Chen HAO, Wen-Hsin CHAN, Chao-Jui WANG
  • Publication number: 20170170067
    Abstract: Provided is a semiconductor device including a substrate, a gate structure, a dielectric layer, an etch stop layer, and an adhesion layer. The gate structure is formed over the substrate. The dielectric layer is formed aside the gate structure. The adhesion layer overlays a top surface of the gate structure and extends to a first top surface of the dielectric layer. The etch stop layer is over the adhesion layer and in contact with a second top surface of the dielectric layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Chi-Ruei Yeh, Wen-Hsin Chan, Kang-Min Kuo
  • Patent number: 9647087
    Abstract: A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate with a gate stack formed on the semiconductor substrate. The method also includes forming a protection layer doped with a quadrivalent element to cover a first doped region formed in the semiconductor substrate and adjacent to the gate stack. The method further includes forming a main spacer layer on a sidewall of the gate stack to cover the protection layer and forming an insulating layer over the protection layer. In addition, the method includes forming an opening in the insulating layer to expose a second doped region formed in the semiconductor substrate and forming one contact in the opening.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mei-Chun Chen, Ching-Chen Hao, Wen-Hsin Chan, Chao-Jui Wang
  • Patent number: 9589915
    Abstract: A semiconductor device includes a substrate defined with a seal ring region and a circuit region, the substrate includes a seal ring structure and an integrated circuit structure, the seal ring structure is disposed in the seal ring region and includes a plurality of stacked conductive layers interconnected by a plurality of via layers, the integrated circuit structure is disposed in the circuit region and includes an active or a passive device; a metal pad disposed over the seal ring region and contacted with the seal ring structure; a passivation layer disposed over the substrate and covering the metal pad; a polymeric layer disposed over the passivation layer and the circuit region; and a molding disposed over the passivation layer and the polymeric layer, wherein the seal ring structure is covered by the molding.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: March 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Wen-Hsin Chan, Chen-Chih Hsieh
  • Publication number: 20170033194
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung CHEN, Kang-Min KUO, Wen-Hsin CHAN