Patents by Inventor Wen-Hsin Wei

Wen-Hsin Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210327778
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 21, 2021
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Publication number: 20210320097
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11101260
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11101140
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Patent number: 11088079
    Abstract: A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Publication number: 20210242173
    Abstract: A semiconductor device and a method of forming the device are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei
  • Patent number: 11069657
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou
  • Patent number: 11062971
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 10985137
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen Hsin Wei
  • Patent number: 10964667
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei
  • Publication number: 20210066151
    Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.
    Type: Application
    Filed: April 12, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Pin Hu, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Wen-Hsin Wei, Chih-Chien Pan
  • Publication number: 20200411440
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai CHENG, Tsung-Shu LIN, Tsung-Yu CHEN, Hsien-Pin HU, Wen-Hsin WEI
  • Publication number: 20200402877
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Chen-Hua Yu, Wen-Hsin Wei, Chi-Hsi Wu, Shang-Yun Hou, Jing-Cheng Lin, Hsien-Pin Hu, Ying-Ching Shih, Szu-Wei Lu
  • Patent number: 10854567
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou, Shin-Puu Jeng, Bruce C. S. Chou
  • Patent number: 10770365
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Pin Hu, Jing-Cheng Lin, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei, Ying-Ching Shih, Chi-Hsi Wu
  • Publication number: 20200219786
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 9, 2020
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Publication number: 20200152602
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate, a first chip stack attached to the substrate, and a second chip stack attached to the substrate. The first chip stack and the second chip stack being attached to a same side of the substrate. The chip package further includes a molding compound layer surrounding the first chip stack and the second chip stack. The molding compound layer covers a topmost surface of the first chip stack. A topmost surface of the molding compound layer is substantially coplanar with a topmost surface of the second chip stack.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou
  • Publication number: 20200126938
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou, Shin-Puu Jeng, Bruce C.S. Chou
  • Publication number: 20200111755
    Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Publication number: 20200035647
    Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 30, 2020
    Inventors: Wei-Ming Chen, Hsien-Pin Hu, Shang-Yun Hou, Wen-Hsin Wei