Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A liquid crystal display panel includes a display area. The display area includes a first scanning line, two second scanning lines, and a number of pixel units arranged in two rows and a number of columns. The number of columns include a number of first columns and a number of second columns arranged alternately. The pixel units arranged in the number of first columns are controlled via the first scanning line, and the two pixel units arranged in each of the number of second columns are controlled via the two second scanning lines correspondingly.

Abstract: A pixel structure using a U-shaped storage capacitance electrode for increasing the aperture ratio thereof is provided. The pixel structure may compensate a variation of the parasitic capacitance (Cgd) between gate and drain for the shift along Y-axis of an exposure machine, so as to reduce the variation of feed-through voltage of pixels.

Abstract: A display panel including a number of data lines and scan lines, a number of first, second, and third switches, and a number of first, second, and third pixels is provided. Each first pixel located at an odd position at a first side of each data line is electrically connected to the corresponding data line through one first switch. Each second pixel located at an even position at the first side of each data line is electrically connected to the corresponding data line through the first, second, and third switches sequentially connected in series. Each third pixel located at a second side of each data line is electrically connected to the corresponding data line through the second and third switches sequentially connected in series. The first, second and third pixels are driven by corresponding scan lines and data lines. A driving method of the display panel is also provided.

Abstract: The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost.

Abstract: A thin film transistor (TFT) array substrate for reducing electrostatic discharge damage includes a substrate, a plurality of pixel units, scan lines and data lines. The substrate has a pixel area and a peripheral area adjacent to the pixel area. The pixel units are disposed in the pixel area. The scan lines and data lines are disposed in the pixel area of the substrate and electrically connected with the pixel units, wherein one end of each scan line extending to the peripheral area is a bonding pad for the scan line. One end of each data line extending to the peripheral area is a bonding pad for the data line. The other end of each data line extending to the peripheral area is an end part of the data line. Particularly, the end part of the data line does not exceed the outmost scan line.

Abstract: An active device array substrate including a substrate, a pixel array, pads, first switching devices, and second switching devices is provided. The pixel array is disposed on a display region of the substrate. The pads, the first and the second switching devices are disposed on a peripheral circuit region of the substrate. The pads and the pixel array are electrically connected. The first and the second switching devices are at the outside of the pads. Each first switching device is electrically connected to one of the pads and has a source, a drain, and a gate electrically connected to the source and the pad. Each second switching device is electrically connected to two adjacent first switching devices and has a gate, a source, and a drain. The source and the drain are electrically connected to the drain and the source of the adjacent first switching device, respectively.

Abstract: A method of adjusting the brightness of a display device is provided. The method includes providing a plurality of saturated level-adjust voltages to various level adjustments of the display device when the central brightness is saturated. Then, a computation of the saturated level-adjust voltage of each level adjustment is carried out to obtain a display voltage of each level adjustment. Thereafter, a computation of the saturated level-adjust voltage, a common voltage and the display voltage of each level adjustment is carried out to obtain a feed-through voltage for each level adjustment. After that, a computation of the feed-through voltage and the saturated level-adjust voltage of each level adjustment is carried out to obtain a liquid crystal capacitance value for each level adjustment. Finally, a simulation of the liquid crystal capacitance value of each level adjustment is carried out to obtain an optimized level-adjust voltage for each level adjustment.

Abstract: A pixel structure includes a first scan line, a second scan line, a third scan line, a data line, a first thin film transistor (TFT), a second TFT, a third TFT, a first pixel electrode and a second pixel electrode. Particularly, the second scan line and the third scan line are electrically connected with each other. The first TFT is electrically connected with the first scan line and the data line. The second TFT is electrically connected with the first TFT and the second scan line. Furthermore, the third TFT is electrically connected with the third scan line and the data line. In addition, the first pixel electrode and the second pixel electrode are respectively electrically connected with the second TFT and the third TFT.

Abstract: An active device array substrate including a substrate, a plurality of active devices, a plurality of the first lead lines, a plurality of the second lead lines and a first floating light-shielding layer is provided. The substrate has a display region and a peripheral circuit region and the active devices are arranged within the peripheral circuit region on the substrate to form an array. Besides, the first lead lines and the second lead lines are disposed within the peripheral circuit region on the substrate. The first floating light-shielding layer is disposed between the first lead lines and covers the part of the first lead lines. Furthermore, the floating light-shielding layer is not connected with any voltage sources completely. Therefore, the active devices array substrate can prevent the light leakage from been resulted between the first lead lines and the power consumption of the active devices array substrate is reduced.

Abstract: A display panel, a display apparatus and the driving method thereof are provided. The gate control signals can interactively control more number of scan lines by disposing corresponding switches between the adjacent scan lines in the display panel, wherein every two scan lines correspond to a gate control signal, so as to reduce the number of the gate driving ICs and the layout space required by the fan out area in the display panel.

Abstract: A thin film transistor (TFT) including a gate, a semiconductor layer, a source and a drain is provided. The gate has a control part, a connection part and a capacitance compensation part. The connection part is disposed between the control part and the capacitance compensation part for joining the two parts together. The semiconductor layer is disposed over the gate, the source and the drain are disposed on the semiconductor layer. An end of the drain overlaps the control part of the gate with a first region for composing a first parasitic capacitance; while another end of the drain overlaps the capacitance compensation part of the gate with a second region for composing a second parasitic capacitance. In a TFT array with the TFT, the sum of the first parasitic capacitance and the second parasitic capacitance is a constant.

Abstract: An active device array substrate including a substrate, a plurality of pixel units, a plurality of first conductive lines, a plurality of second conductive lines, a lead line, at least one first electrostatic discharge protection circuit, and at least one second electrostatic discharge protection circuit is provided. The pixel units are arranged on the substrate. Additionally, the first conductive lines and the second conductive lines are disposed on the substrate and electrically connected to the pixel units respectively. Moreover, the lead line crosses the first conductive lines. The first electrostatic discharge protection circuit is disposed at one side of the lead line, and the second electrostatic discharge protection circuit corresponding to the first electrostatic discharge protection circuit is disposed at the other side of the lead line.

Abstract: A pixel structure using a U-shaped storage capacitance electrode for increasing the aperture ratio thereof is provided. The pixel structure may compensate a variation of the parasitic capacitance (Cgd) between gate and drain for the shift along Y-axis of an exposure machine, so as to reduce the variation of feed-through voltage of pixels.

Abstract: An active device array substrate including a substrate, a plurality of active devices, a plurality of the first lead lines, a plurality of the second lead lines and a first floating light-shielding layer is provided. The substrate has a display region and a peripheral circuit region and the active devices are arranged within the peripheral circuit region on the substrate to form an array. Besides, the first lead lines and the second lead lines are disposed within the peripheral circuit region on the substrate. The first floating light-shielding layer is disposed between the first lead lines and covers the part of the first lead lines. Furthermore, the floating light-shielding layer is not connected with any voltage sources completely. Therefore, the active devices array substrate can prevent the light leakage from been resulted between the first lead lines and the power consumption of the active devices array substrate is reduced.

Abstract: A thin film transistor array comprising a substrate, thin film transistors, pixel electrodes, common lines, and auxiliary electrodes disposed on the substrate is provided. The substrate has a plurality of pixel regions, and each of the thin film transistors, pixel electrodes, and auxiliary electrodes are disposed in each pixel region. In each pixel region, the pixel electrode is covered over the common line and is electrically connected to the thin film transistor. The auxiliary electrode is located between the pixel electrode and the common line, and the area of the overlapping region between the auxiliary electrode and the common line is L×H, while the sum of the side lengths of the overlapping region is more than 2L×2H, wherein L and H are both positive real numbers. The individual feed-through voltages in each pixel regions in the thin film transistor array are the same.

Abstract: A liquid crystal display panel having scan lines, data lines and pixel units is provided. The scan lines and the data lines crisscross each other on a substrate. Each pixel unit is electrically connected to one of the scan lines and one of the data lines. Each pixel unit includes an active device, a liquid crystal capacitor and a storage capacitor. The active device is disposed on the substrate. The liquid crystal capacitor is electrically connected to the active device. The storage capacitor is electrically connected to the liquid crystal capacitor. The capacitances of the storage capacitors decrease inward from the two sides of the liquid crystal display panel. The capacitance is varied in such a way that the voltage difference of the liquid crystal in the positive and the negative frame at the same brightness level is equalized to prevent the liquid crystal display panel from flickering.

Abstract: A pixel structure and a method of repairing the same are provided. The pixel structure includes a scan line, a data line, a thin film transistor, a pixel electrode, a common line and a dielectric layer. The common line adjacent to the data line serves as a repairing section, the repairing section includes a first repairing terminal, a second repairing terminal and a cutting region, the first repairing terminal and the second repairing terminal are disposed under the data line and the cutting region is disposed between the first repairing terminal and the section of the common line that does not extend along the data line, and the pixel electrode does not cover the cutting region.

Abstract: A pixel structure comprising a substrate, a first metal layer, a first dielectric layer, a semiconductor layer, a second metal layer and a pixel electrode is provided. The first metal layer, disposed on the substrate, includes a gate and a scan line. The first dielectric layer covers the first metal layer. The semiconductor layer is disposed on the first dielectric layer above the gate. The second metal layer includes a source, a drain and a data line connected with the source. The pixel electrode is electrically connected with the drain. Wherein, the drain has a main body and an extension portion projecting out of the scan line. The main body has a first length (L1). The interface of the extension portion and the scan line is a second length (L2). The L1/L2 is predetermined such that the Cgd of the pixel structure is fixed.

Abstract: A thin film transistor (TFT) including a gate, a semiconductor layer, a source and a drain is provided. The gate has a control part, a connection part and a capacitance compensation part. The connection part is disposed between the control part and the capacitance compensation part for joining the two parts together. The semiconductor layer is disposed over the gate, the source and the drain are disposed on the semiconductor layer. An end of the drain overlaps the control part of the gate with a first region for composing a first parasitic capacitance; while another end of the drain overlaps the capacitance compensation part of the gate with a second region for composing a second parasitic capacitance. In a TFT array with the TFT, the sum of the first parasitic capacitance and the second parasitic capacitance is a constant.