Abstract: A method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.

Abstract: A semiconductor device includes a substrate, at least one via, a liner layer and a conductive layer. The substrate includes an electronic circuitry. The at least one via passes through the substrate. The at least one via includes a plurality of concave portions on a sidewall thereof. The liner layer fills in the plurality of concave portions of the at least one via. The conductive layer is disposed on the sidewall of the at least one via, covers the liner layer, and extends onto a surface of the substrate. The thickness of the conductive layer on the sidewall of the at least one via is varied.

Abstract: A semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.

Abstract: Protection from electrostatic discharge (ESD) events is provided by forming leading points of discharge (LPoD) structures on a semiconductor die or on a composite die. The LPoD structures may comprise an upper protrusion portion on an ESD path metal structure, intermediate metallic material portions, solder material portions having a greater height than normal solder material portions that are not provided with ESD protection, or a elongated metal bar structure. The LPoD structures may be used for anisotropic etch process for forming via cavities, bonding processes using solder material portions, bonding processes using metal-to-metal bonding, and/or solder ball attachment processes.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: Semiconductor structures and methods are provided. An exemplary semiconductor structure includes a contact pad over a substrate, an under-bump metallization (UBM) layer over the contact pad, a metal pillar over first UBM layer and electrically coupled to the contact pad via the UBM layer, and a solder cap on the metal pillar. The metal pillar comprises copper, and a percentage of (111) crystal orientation of the copper is 90% or more.

Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Abstract: Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate, active devices and transparent conductive patterns. The active devices are formed on the semiconductor substrate. The transparent conductive patterns are formed over the active devices and electrically connected to the active devices. The transparent conductive patterns are made of a metal oxide material. The metal oxide material has a first crystalline phase with a prefer growth plane rich in oxygen vacancy, and has a second crystalline phase with a prefer growth plane poor in oxygen vacancy.

Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.

Abstract: Microelectromechanical devices and methods of manufacture are presented. Embodiments include bonding a mask substrate to a first microelectromechanical system (MEMS) device. After the bonding has been performed, the mask substrate is patterned. A first conductive pillar is formed within the mask substrate, and a second conductive pillar is formed within the mask substrate, the second conductive pillar having a different height from the first conductive pillar. The mask substrate is then removed.