Abstract: In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

Abstract: A method of forming a package assembly includes forming a no-flow underfill layer on a substrate. The method further includes attaching a semiconductor die to the substrate. The semiconductor die comprises a bump and a molding compound layer in physical contact with a lower portion of the bump. An upper portion of the bump is in physical contact with the no-flow underfill layer.

Abstract: An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Abstract: A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Abstract: A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Abstract: A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer.

Abstract: A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract: A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.

Abstract: Methods of packaging and dicing semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging and dicing semiconductor devices includes a first cutting process performed on a wafer to form a groove passing through a passivation layer and an interconnect structure on a scribe line region and a portion of a semiconductor substrate on the scribe line region. Next, a molding compound layer is formed on a frontside of the wafer to fill the groove. After performing a grinding process on a backside of the wafer to thin down the semiconductor substrate, a second cutting process is performed on the wafer to separate the individual dies. The second cutting process cuts through the molding compound layer in the groove and the semiconductor substrate underlying the groove.

Abstract: The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.

Abstract: A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material.

Abstract: An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract: A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.

Abstract: A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer.

Abstract: Methods and apparatus for a forming molded underfills. A method is disclosed including loading a flip chip substrate into a selected one of the upper mold chase and lower mold chase of a mold press at a first temperature; positioning a molded underfill material in the at least one of the upper and lower mold chases while maintaining the first temperature which is lower than a melting temperature of the molded underfill material; forming a sealed mold cavity and creating a vacuum in the mold cavity; raising the temperature of the molded underfill material to a second temperature greater than the melting point to cause the molded underfill material to flow over the flip chip substrate forming an underfill layer and forming an overmolded layer; and cooling the flip chip substrate to a third temperature substantially lower than the melting temperature of the molded underfill material. An apparatus is disclosed.