Abstract: Embodiments of a method for packaging Integrated Circuit (IC) dies and an IC device are described. In an embodiment, a method for packaging IC dies involves creating openings on a substrate, where side surfaces of the openings on the substrate are covered by metal layers, placing the IC dies into the openings on the substrate, applying a second metal layer to the substrate, where the IC dies are electrically connected to at least a portion of the second metal layer, and cutting the substrate into IC devices.

Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.

Abstract: A semiconductor device includes a device die having a top surface, a bottom surface, and sidewalls between the top and bottom surfaces. A first protective layer covers at least the top surface and the sidewalls of the die. A thickness of the first protective layer on the sidewalls near the top surface is greater than a thickness of the first protective layer on the sidewalls die near the bottom surface.

Abstract: Embodiments of a method for packaging Integrated Circuit (IC) dies and an IC device are described. In an embodiment, a method for packaging IC dies involves creating openings on a substrate, where side surfaces of the openings on the substrate are covered by metal layers, placing the IC dies into the openings on the substrate, applying a second metal layer to the substrate, where the IC dies are electrically connected to at least a portion of the second metal layer, and cutting the substrate into IC devices.

Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.

Abstract: An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode.

Abstract: An image processing unit including an always on circuit block and a non-always on circuit block is provided. When operating under a first operation mode, the non-always on circuit block receives a bias voltage from a power supply unit, so as to perform an image processing operation on an image input signal. When operating under a second operation mode, the non-always on circuit block stops receiving the bias voltage from the power supply unit, so as to stop the image processing operation, and at least a microcontroller of the non-always on circuit block is powered down. One of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying the bias voltage to the non-always on circuit block according an event trigger signal, such that the non-always on circuit block enters the second operation mode from the first operation mode.

Abstract: In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode.

Abstract: An image processing method for a display device, for enhancing image quality, includes receiving video signals, sequentially generating a plurality of image data according to the video signals, and sequentially displaying the plurality of image data on a panel of the display device. Each of the plurality of image data includes a frame data and a low-gray-level frame data respectively corresponding to a frame output duration and a vertical blanking duration in a timing sequence of the video signals.

Abstract: A three-dimensional (3D) video processing device capable of avoiding crosstalk between adjacent frames includes a video processing circuit and a control circuit. The video processing circuit is configured to generate a 3D video signal having a first frame timing. The 3D video signal is used to control a panel to update, to thereby display 3D video frames in accordance with a second frame timing which is a delayed version of the first frame timing. The control circuit is utilized for generating a backlight control signal. A switching timing of the backlight control signal is determined according to the second frame timing.

Abstract: A method and an apparatus for interlace scanning video signal frequency multiplication are provided. The method includes the following steps: first, removing a part of a first vertical synchronous signal (V-sync signal) which is asynchronous with a first horizontal synchronous signal (H-sync signal); next, capturing a first field and a second field from an interlace scan video signal according to the first V-sync signal obtained in the previous step; performing a frequency multiplication on a frame made up by the first and second fields, and producing a second V-sync signal and a second H-sync signal; finally, compensating for the second V-sync signal on a border between two fields of the frame after the frequency multiplication according to the second H-sync signal. Thereby, the method can be used to perform frequency multiplication using a line buffer instead of a frame buffer, to output through interface scanning without sacrificing image quality.

Abstract: In a normal mode, the power supply is fed back in a close loop, but in a power saving mode, the power supply is fed back in an open loop. When it is detected that the power supply is continuously fed back in the open loop and in a substantially zero output status, the power supply circuit enters a power down status. If the back-stage circuit needs power supply again, then the feedback is switched to the close loop and the power supply circuit enters the normal mode.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: To reduce production cost, the present invention provides a microprocessor device for an LCD controller, which includes a memory, a first processing unit, a second processing unit, a first arbiter and a second arbiter. The memory is utilized for storing data. The first processing unit is utilized for executing a first program. The second processing unit is utilized for executing a second program. The first arbiter is coupled to the first processing unit and the second processing unit and utilized for deciding an operation order for the first processing unit and the second processing unit. The second arbiter is coupled to the first processing unit, the second processing unit and the memory and utilized for deciding a memory accessing order for the first processing unit and the second processing unit.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: A data access control system of a memory includes a micro-processor, having a micro-controller, a command decoder, and a memory interface. The data access control system can be used to control display driving of a display system. The command decoder is used to decode the content of a data access command. A memory unit is configured into a first region for storing a first-type data being stored in a memory manner, and a second region for storing a second-type data being stored in a simulation manner of the memory. A bus is connected between the micro-processor and the memory unit, for performing data transmission. The micro-processor uses the memory interface to write data into the first region of the memory unit, and uses the command decoder to convert the nonvolatile data and write into the second region of the memory unit.

Abstract: An image processing method for a display device, for enhancing image quality, includes receiving video signals, sequentially generating a plurality of image data according to the video signals, and sequentially displaying the plurality of image data on a panel of the display device. Each of the plurality of image data includes a frame data and a low-gray-level frame data respectively corresponding to a frame output duration and a vertical blanking duration in a timing sequence of the video signals.

Abstract: An automatic clamping analog-to-digital converter (A/D converter) is provided, which includes an A/D converter, a switch, a comparator, a bidirectional counter, and a digital-to-analog converter (D/A converter). Wherein, the A/D converter receives an analog signal from a node, and then converts the analog signal into a digital signal according to a DC offset level. The switch is coupled between the node and a fixed voltage level, and is turned on or off according to a clamping signal. The comparator outputs a compare signal according to a comparison result between the digital signal and an offset value. The bidirectional counter outputs a count, and increases or decreases the count according to the compare signal. The D/A converter converts the count into the DC offset level and provides the DC offset level to the A/D converter.

Abstract: A method and an apparatus for interlace scanning video signal frequency multiplication are provided. The method includes the following steps: first, removing a part of a first vertical synchronous signal (V-sync signal) which is asynchronous with a first horizontal synchronous signal (H-sync signal); next, capturing a first field and a second field from an interlace scan video signal according to the first V-sync signal obtained in the previous step; performing a frequency multiplication on a frame made up by the first and second fields, and producing a second V-sync signal and a second H-sync signal; finally, compensating for the second V-sync signal on a border between two fields of the frame after the frequency multiplication according to the second H-sync signal. Thereby, the method can be used to perform frequency multiplication using a line buffer instead of a frame buffer, to output through interface scanning without sacrificing image quality.