Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: The present invention relates to a fiber composite material and a method for producing the fiber composite material. The method for producing the fiber composite material includes a hydrolysis step of a silicon precursor having an alkoxy group, an in-situ condensation step and a drying step. A specific silicon precursor having a secondary amino group and alkyl groups is used therein, as well as a specific weight ratio of the silicon precursor to a fiber material, the in-situ condensation step can be performed in the absence of organic solvents in the method for producing the fiber composite material, and a hydrophobic modification on silicon-based gels can be performed, thereby simplifying the process, decreasing a thermal conductivity of the resulted fiber composite material and preventing drop dust of the resulted fiber composite material.

Abstract: The present invention relates to silicon-based powders and a method for producing the silicon-based powders. The method for producing the silicon-based powders includes a hydrolysis step of a silicon precursor having an alkoxy group, a condensation step and a drying step. By a specific weight ratio of water to the silicon precursor having the alkoxy group and a silicon precursor having a secondary amino group and an alkyl group, in the method for producing the silicon-based powders, the condensation step can be performed without organic solvents, and a modification on silicon-based gels can be performed to enhance a safety of processes and a hydrophobicity of the resulted silicon-based powders, and decrease a thermal conductivity and a bulk density of the resulted silicon-based powders.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract: A method for forming metal contacts within a semiconductor device includes forming a first-layer contact into a first dielectric layer that surrounds at least one gate electrode, the first-layer contact extending to a doped region of an underlying substrate. The method further includes forming a second dielectric layer over the first dielectric layer and forming a second-layer contact extending through the second dielectric layer to the first-layer contact.

Abstract: A method for fabricating a semiconductor product includes applying a photo-resist layer to a substrate, the photo-resist layer including a higher acid concentration at an upper portion of the photo-resist layer than at a lower portion of the photo-resist layer. The method also includes exposing the photo-resist layer to a light source through a mask including a feature, the photo-resist layer including a floating, diffusing acid that will diffuse into a region of the photo-resist layer affected by the feature while not diffusing into a feature formed by the mask.

Abstract: A panel and housing assembly includes a housing provided with a locking slot, a panel provided with a receiving space, and a locking tenon mounted between the housing and the panel and having a first end provided with an elastic portion received in the receiving space of the panel and a second end provided with a locking portion inserted into and locked in the locking slot of the housing. Thus, the panel is locked onto the housing by compressing the locking tenon and unlocked from the housing by pressing the press plate of the locking tenon so that the panel and housing assembly is assembled and disassembled easily and quickly without needing aid of any hand tool, thereby facilitating a user assembling and disassembling the panel and housing assembly.