Patents by Inventor Wen-Hwa Chen

Wen-Hwa Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190162886
    Abstract: An invisible light blocking structure includes a first transparent substrate, a metal layer, a transparent protecting layer and an invisible light blocking unit. The first transparent substrate has a first bottom side and a first upper side. The metal layer is disposed on the first bottom side and has a first metal side facing away from the first transparent substrate. The first upper side faces away from the metal layer. The transparent protecting layer is disposed on the first metal side. The transparent protecting layer has a first protecting side facing away from the first transparent substrate. The invisible light blocking unit is disposed on at least one of a first protecting side and the first upper side. The invisible light blocking unit has cesium tungstate.
    Type: Application
    Filed: September 25, 2018
    Publication date: May 30, 2019
    Inventors: Horng-Hwa LU, Wen-Fu CHEN, Wen-Liang CHEN, Yin-Hsien LAI
  • Patent number: 8948474
    Abstract: A quantification method and an imaging method are disclosed, capable of quantifying the margin feature, the cysts feature, the calcifications feature, the echoic feature and the heterogenesis feature of a tumor, and capable of imaging the margin feature, the cysts feature, the calcifications feature and the heterogenesis feature of a tumor. The quantification method and the imaging method calculate the moving variance of the gray scale of each of the pixel points based on the gradient value of the gray scale of these pixel points. Then, depending on the purpose of the quantification method or the imaging method, the maximum value, the minimum value, the mean value, and the standard deviation of the moving variance of the gray scale of these pixel points are calculated, respectively. At final, with the definition of the threshold value and the imaging rule, the above features of the tumor are quantified or imaged.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 3, 2015
    Assignee: Amcad BioMed Corporation
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Po Wei Tsai, Chung Wei Liu, Hsin-Jung Wu
  • Patent number: 8747925
    Abstract: The present invention provides a pharmaceutical composition for treating diabetes comprising Ramulus Cinnamomi, Radix et Rhizoma Rhei, Semen Persicae, Radix Rhizoma Glycyrrhizae, and Cordyceps. The use of the composition for the manufacture of a medicament for treating type II diabetes is also provided.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: June 10, 2014
    Assignee: Phytohealth Corporation
    Inventors: Chen-Chia Lee, Wen-Hwa Chen, Tsung-Shann Jiang, Yu-Ju Lai, Shih-Jen Wang
  • Patent number: 8572006
    Abstract: The present invention relates to a method for multi-layer classifier applying on a computer readable medium for classifying multiple image samples. The method at least comprising the following steps: (a) receiving a plurality of samples; (b) providing a plurality of attributes, and evaluating a significance of the attributes by a selection criterion; (c) selecting at least one cut-point to establish a discriminant analysis model; (d) proceeding a step of evaluating a performance of the discriminant analysis model by adding the attributes to the discriminant analysis model; and (e) providing a stop criterion. The present invention also provides a computer readable medium for classifying multiple image samples by using the method for multi-layer classifier.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: October 29, 2013
    Assignee: AmCad BioMed Corporation
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Hsin-Jung Wu
  • Patent number: 8374892
    Abstract: The present invention related to a method for retrieving a tumor contour of an image processing system that includes a memory storing a grayscale image and a processor, comprising: receiving an input tumor contour of the grayscale image; defining a tumor contour annular region and a plurality of reference segments of the grayscale image, wherein the input tumor contour is in the tumor contour annular region, and each of the plurality of reference segments is across the tumor contour annular region and includes a plurality of measured points; retrieving a tumor contour suggestion point on each of the plurality of reference segments; and linking all the tumor contour suggestion points on all of the reference segments, for forming the tumor contour. Accordingly, by applying the method of the present invention, a doctor can rapidly and accurately identify the contour of a tumor in a grayscale image.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 12, 2013
    Assignee: AmCad BioMed Corporation
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Po Wei Tsai
  • Publication number: 20120321731
    Abstract: The present invention provides a pharmaceutical composition for treating diabetes comprising Ramulus Cinnamomi, Radix et Rhizoma Rhei, Semen Persicae, Radix Rhizoma Glycyrrhizae, and Cordyceps. The use of the composition for the manufacture of a medicament for treating type II diabetes is also provided.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 20, 2012
    Applicant: Phytohealth Corporation
    Inventors: Chen-Chia Lee, Wen-Hwa Chen, Tsung-Shann Jiang, Yu-Ju Lai, Shih-Jen Wang
  • Patent number: 8134823
    Abstract: In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: March 13, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen, Su-Tsai Lu
  • Patent number: 7999350
    Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: August 16, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Su-Tsai Lu, Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen
  • Publication number: 20110182522
    Abstract: The present invention relates to a method for multi-layer classifier applying on a computer readable medium for classifying multiple image samples. The method at least comprising the following steps: (a) receiving a plurality of samples; (b) providing a plurality of attributes, and evaluating a significance of the attributes by a selection criterion; (c) selecting at least one cut-point to establish a discriminant analysis model; (d) proceeding a step of evaluating a performance of the discriminant analysis model by adding the attributes to the discriminant analysis model; and (e) providing a stop criterion. The present invention also provides a computer readable medium for classifying multiple image samples by using the method for multi-layer classifier.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Hsin-Jung Wu
  • Publication number: 20110182489
    Abstract: The present invention related to a method for retrieving a tumor contour of an image processing system that includes a memory storing a grayscale image and a processor, comprising: receiving an input tumor contour of the grayscale image; defining a tumor contour annular region and a plurality of reference segments of the grayscale image, wherein the input tumor contour is in the tumor contour annular region, and each of the plurality of reference segments is across the tumor contour annular region and includes a plurality of measured points; retrieving a tumor contour suggestion point on each of the plurality of reference segments; and linking all the tumor contour suggestion points on all of the reference segments, for forming the tumor contour. Accordingly, by applying the method of the present invention, a doctor can rapidly and accurately identify the contour of a tumor in a grayscale image.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Po Wei Tsai
  • Publication number: 20110181614
    Abstract: A quantification method and an imaging method are disclosed, capable of quantifying the margin feature, the cysts feature, the calcifications feature, the echoic feature and the heterogenesis feature of a tumor, and capable of imaging the margin feature, the cysts feature, the calcifications feature and the heterogenesis feature of a tumor. The quantification method and the imaging method calculate the moving variance of the gray scale of each of the pixel points based on the gradient value of the gray scale of these pixel points. Then, depending on the purpose of the quantification method or the imaging method, the maximum value, the minimum value, the mean value, and the standard deviation of the moving variance of the gray scale of these pixel points are calculated, respectively. At final, with the definition of the threshold value and the imaging rule, the above features of the tumor are quantified or imaged.
    Type: Application
    Filed: January 25, 2010
    Publication date: July 28, 2011
    Inventors: King Jen Chang, Wen Hwa Chen, Argon Chen, Chiung Nein Chen, Ming Chih Ho, Hao Chih Tai, Ming Hsun Wu, Po Wei Tsai, Chung Wei Liu, Hsin-Jung Wu
  • Publication number: 20090257169
    Abstract: In order to avoid the capacitors in a stacked capacitor structure suiting a miniaturization process from collapsing to cause a short-circuit, separated reinforced structures are used and disposed at the outer-sidewalls of the capacitor, which not only reduces the space occupied by the reinforced structure to increase the surface areas of the upper electrode and the lower electrode of the capacitor, but also allows the capacitor to be deflected but collapse-proof and there are more spaces between the capacitors, so as to solve the filling difficulty problem due to a too small filling space in a successive process of depositing conductive material into the filling space.
    Type: Application
    Filed: February 5, 2009
    Publication date: October 15, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen, Su-Tsai Lu
  • Publication number: 20090224362
    Abstract: After a fabrication process intended to miniaturize semiconductor devices, a surface area of a stack capacitor in a random access memory (RAM) is significantly reduced and capacity thereof is thus decreased, which in turn causes the capacitor not able to function properly. The present invention provides a composite lower electrode structure consisting of an exterior annular pipe and a central pillar having concave-convex surfaces to increase a surface area of the capacitor within a limited memory cell so as to enhance the capacity. To reinforce intensity of a structure of the capacitor, the exterior annular pipe has an elliptic radial cross section and a thicker thickness along a short axis direction.
    Type: Application
    Filed: September 8, 2008
    Publication date: September 10, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Su-Tsai Lu, Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen
  • Publication number: 20090184393
    Abstract: The structure strength of a memory capacitor is reduced as the height of the memory capacitor is increased, which results in collapse and a short circuit. This invention provides a capacitor with a special reinforced structure outside, wherein the reinforced structure extends upward from the bottom of the lower electrode of the capacitor to a height, thus reducing the deformation caused by the process loading and supplying sufficient capacitance. In addition, the height of the reinforced structure is adaptable to requirement. Thereby, even when the capacitors are connected with one another because the capacitors collapse, the capacitors are prevented from malfunction. Moreover, the reinforced structures can be connected to one another or not, and thus the structure strength of the capacitor arrays is increased. Besides, the process is simplified and the cost is also reduced.
    Type: Application
    Filed: August 20, 2008
    Publication date: July 23, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wen-Hwa Chen, Hsien-Chie Cheng, Yun-Chiao Chen, Su-Tsai Lu
  • Patent number: 6781225
    Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are connected to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: August 24, 2004
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Publication number: 20030116862
    Abstract: An integrated circuit chip with ball-grid array solder balls is packaged as a module without being sealed in protective glue. The IC chip is mounted on an insulating substrate with pads to support the solder balls. The pads are conducted to a second set of pads along the periphery of the substrate. Leads are pressed against the second set of pads for external connections. A second IC chip may be pressed against the other side of the substrate to increase the external connections.
    Type: Application
    Filed: December 6, 2002
    Publication date: June 26, 2003
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Publication number: 20020050378
    Abstract: The IC chips of a multiple IC chip module are mounted in stack in a ceramic substrate, which has good heat dissipating capability. At least one IC chip is mounted on top of the ceramic substrate and at least one other IC chip is mounted at the bottom of the ceramic substrate. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one of the surfaces and solder connection at the bottom. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
    Type: Application
    Filed: May 24, 2001
    Publication date: May 2, 2002
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6137174
    Abstract: A package for multiple IC chip module. The IC chip is attached to electric wires on ceramic substrate which has good heat dissipating capability. The bonding pads along the periphery of the ceramic substrate are lead-bonded to a second substrate with printed wiring on at least one side of the surfaces and ball grid array at the bottom surface. Double-sided printed wiring can be used to provide multiple-layered interconnection. The IC chip is separated from the second substrate by a resin to cushion the stress due to difference in thermal expansion coefficients of the IC chip and the second substrate.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: October 24, 2000
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6034425
    Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are butted together to save space. The bonding pads for the lower IC chip or chips are placed along the edges not butted with one another. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be placed at the top of the IC chips away from the ball grid array.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: March 7, 2000
    Assignee: ChipMOS Technologies Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng
  • Patent number: 6023097
    Abstract: A micro ball grid array package is devised for a multiple-chip module (MCM). The IC chips in the package are stacked to save space. The bonding pads for the lower IC chip or chips are placed along the edges where the pads are not masked by the stacking of the upper chip or chips. When there are more than one chip at each level of the stacking, the IC chips at each level are butted with each other to further save space. The bonding pads of the chips are wire-bonded to a printed wiring plate, which has via holes through the printed wiring plate for connection to the ball grid array at the other side of the printed wiring plate and for surface mounting to a printed circuit board. A heat dissipating plate may be inserted at the bottom of the IC chips away from the stacking surface.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: February 8, 2000
    Assignee: ChipMOS Technologies, Inc.
    Inventors: Kuo-Ning Chiang, Wen-Hwa Chen, Kuo-Tai Tseng