Patents by Inventor Wen-Hwa M. Chu

Wen-Hwa M. Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Verification method with the implementation of well voltage pseudo diodes
    Patent number: 7895554
    Abstract: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Wen-Hwa M. Chu, Shaibal Barua, Lily X. Springer, James Homack
  • Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
    Patent number: 7562315
    Abstract: Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: July 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Lily X. Springer, Haim Horovitz, Robert Graham Shaw, Jr., Sameer Pendharkar, Wen-Hwa M. Chu, Paul C. Mannas
  • VERIFICATION METHOD WITH THE IMPLEMENTATION OF WELL VOLTAGE PSEUDO DIODES
    Publication number: 20080189666
    Abstract: A method of verifying consistency between a circuit schematic and a corresponding integrated circuit layout is disclosed. The method includes identifying a voltage condition associated with a portion of the circuit schematic, and assigning a pseudo diode to the portion of the circuit schematic that is uniquely associated with the identified voltage condition. The method further includes coding a pseudo layer associated with an integrated circuit layout of the circuit schematic in accordance with content of the assigned pseudo diode, and verifying consistency between the circuit schematic and the corresponding integrated circuit layout by extracting the pseudo layer from the integrated circuit layout and comparing information of the pseudo layer to the assigned pseudo diode in the circuit schematic.
    Type: Application
    Filed: December 21, 2007
    Publication date: August 7, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Wen-Hwa M. Chu, Shaibal Barua, Lily X. Springer, James Homack