Abstract: A display control apparatus is provided to generate a scaled video output overlaid onto a computer graphics output. The display control apparatus includes a timing generator, adapted to receive a horizontal synchronization signal of the computer graphics output and the pixel number of horizontal scan line of the scaled video output, for generating a pixel clock of scaled video output and a horizontal lock signal; a scaling buffer, storing a video digital pixel data and having an output port generating the scaled video output, responsive to the pixel clock of scaled video output; an overlay controller, coupled to a controller bus and receiving an analog pixel data of the computer graphics output and, responsive to the pixel clock of scaled video output, the horizontal lock signal and a vertical synchronization signal of the computer graphics output, for overlaying the scaled video output onto the computer graphics output.

Abstract: The invention inputs a single timing clock. Through procedure of mode setting, the invention generates the required timings corresponding to the display mode selected. In the invention, a programmable mode register, a mode decoder, a pixel timing generator, a horizontal timing generator, a vertical timing generator, a composite timing generator, AND gate, EXCLUSIVE NOR gate, and a selector are provided. The invention may generate the required timings for NTSC interlace mode, NTSC non-interlace mode, PAL interlace mode, PAL non-interlace mode, VGA 60 Hz progressive mode and VGA 50 Hz progressive mode.