Abstract: Some embodiments relate to a pixel array, including: a substrate including a first side and a second side opposite the first side; a plurality of photodetectors in the substrate, the plurality of photodetectors symmetrically disposed around a middle axis between the plurality of photodetectors, where the middle axis is perpendicular to the first side and the second side; a first doped region at the middle axis between the plurality of photodetectors and on the first side of the substrate; a frontside deep trench isolation (DTI) structure on the first side of the substrate and extending directly between photodetectors of the plurality of photodetectors; and a backside DTI structure on the second side of the substrate and spacing the frontside DTI structure from the middle axis.

Abstract: Some embodiments relate to A deep trench isolation (DTI) structure, including: a DTI core extending into a substrate; a first film surrounding the DTI core and having a first material with a first conduction band at a first band energy; a second film between the first film and the DTI core, the second film having a second material with a second conduction band at a second band energy less than the first band energy; and a third film between the second film and the DTI core, the third film having a third material with a third conduction band at a third band energy greater than the second band energy.

Abstract: Some embodiments relate to an integrated circuit (IC) device including a first IC die and a second IC die. The first IC die includes first and second conductive structures at a first surface of the first IC die, and the first and second conductive structures are laterally separated by a first dielectric structure. The second IC die includes third and fourth conductive structures at a first surface of the second IC die, and the third and fourth conductive structures are laterally separated by a second dielectric structure. The first surface of the first IC die faces the first surface of the second IC die such that the first conductive structure vertically contacts the third conductive structure to form a first capacitor electrode, and the second conductive structure vertically contacts the fourth conductive structure to form a second capacitor electrode. The first and second capacitor electrodes form a capacitor.

Abstract: The present disclosure relates to a multi-dimensional image sensor integrated chip (IC) structure. The multi-dimensional image sensor IC structure includes a plurality of image sensing elements disposed within a plurality of pixel regions arranged in a pixel array of a first integrated chip (IC) tier. The plurality of pixel regions include a plurality of active pixel regions and one or more dummy pixel regions. A plurality of pixel support devices are disposed on a second substrate within a second IC tier that is bonded to the first IC tier. A plurality of logic devices are disposed within a third IC tier that is bonded to the second IC tier. A through substrate via (TSV) extends vertically through the second substrate laterally outside of the plurality of pixel support devices and directly below the pixel array.

Abstract: Various embodiments of the present disclosure are directed to a stacked complementary metal-oxide semiconductor (CMOS) image sensor. A first integrated circuit (IC) chip and a second IC chip are vertically stacked. A pixel sensor spans the first and second IC chips. The pixel sensor comprises a first transfer transistor and a photodetector that are at the first IC chip, and further comprises a source-follower transistor, a transistor capacitor, and a second transfer transistor that are at the second IC chip. The transistor capacitor and the second transfer transistor are electrically coupled in series from a source/drain region of the first transfer transistor to a gate electrode of the source-follower transistor.

Abstract: A p-type doping region around an isolation structure provides additional electrical isolation between pixel sensors of a pixel array. As a result, current leakage from a floating node of one pixel sensor into another is reduced. Therefore, dark current is reduced, and performance of the pixel array is improved. Additionally, pixel noise caused by electrons trapped in the isolation structure may be reduced.

Abstract: A semiconductor image-sensing structure includes a reflective grid and a reflective shield disposed over a substrate. The reflective grid is disposed in a first region, and the reflective shield is disposed in a second region separated from the first region. A thickness of the reflective shield is greater than a thickness of the reflective grid.

Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.

Abstract: An optical device and a method of fabricating the same are disclosed. The optical device includes a first die layer and a second die layer. The first die layer includes a first substrate having a first surface and a second surface opposite to the first surface, first and second pixel structures, an inter-pixel isolation structure disposed in the first substrate and surrounding the first and second pixel structures, and a floating diffusion region disposed in the first substrate and between the first and second pixel structures. The second die layer includes a second substrate having a third surface and a fourth surface opposite to the third surface and a pixel transistor group disposed on the third surface of the second substrate and electrically connected to the first and second pixel structures.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a plurality of gate structures arranged along a first side of a substrate within a plurality of pixel regions. An etch block structure is arranged on the first side of the substrate between neighboring ones of the plurality of gate structures. A contact etch stop layer (CESL) is arranged on the etch block structure between the neighboring ones of the plurality of gate structures. An isolation structure is disposed between one or more sidewalls of the substrate and extends from a second side of the substrate to the first side of the substrate. The etch block structure is vertically between the isolation structure and the CESL.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: A method of manufacturing an image sensor structure includes forming an isolation structure in a substrate to divide the substrate into a first region and a second region, forming a first light sensing region in the first region and a second light sensing region in the second region, forming a first gate structure over the first light sensing region and a second gate structure over the second light sensing region, forming gate spacers on sidewalls of the first and second gate structures, and depositing a blocking layer on sidewalls of the gate spacers. The blocking layer has an opening positioned between the first and second gate structures. A source/drain structure is formed directly under the opening in the blocking layer. The method also includes forming an interlayer dielectric layer over the first and second gate structures and the blocking layer.

Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a plurality of photodetectors disposed within a substrate. The photodetectors are disposed respectively within a plurality of pixel regions. A floating diffusion node is disposed along a front-side surface of the substrate at a middle region of the plurality of pixel regions. A plurality of well regions is disposed within the substrate at corners of the plurality of pixel regions. An isolation structure extends into a back-side surface of the substrate. The isolation structure comprises a plurality of elongated isolation components disposed between adjacent pixel regions, a middle isolation component aligned with the floating diffusion node, and multiple peripheral isolation components aligned with the plurality of well regions. The elongated isolation components have a first height and the middle and peripheral isolation components have a second height less than the first height.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor comprise a substrate having a first region and a second region. A first gate overlies the first region. A second gate overlies the second region. A deep trench isolation (DTI) structure is in the substrate and laterally between the first region and the second region. A first floating diffusion node is in the first region. A second floating diffusion node is in the second region. An interlayer dielectric (ILD) structure is over the substrate. A dielectric structure is between the ILD structure and the substrate. The dielectric structure is laterally between the first and second floating diffusion nodes. The dielectric structure is laterally spaced from the first and second gates. The dielectric structure overlies the DTI structure. A width of the dielectric structure is greater than a width of the DTI structure.

Abstract: The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.

Abstract: A semiconductor image sensing structure includes a substrate having a first region and a second region, a metal grid in the first region, and a hybrid metal shield in the second region. The hybrid metal shield includes a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer. An included angle of the second metallization layer is between approximately 40° and approximately 60°.

Abstract: A method for wafer bonding includes receiving a layout of a bonding layer with an asymmetric pattern, determining whether an asymmetry level of the layout is within a predetermined range by a design rule checker, modifying the layout to reduce the asymmetry level of the layout if the asymmetry level is beyond the predetermined range. The method also includes outputting the layout in a computer-readable format.

Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.

Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.