Patents by Inventor Wen-I Hsu

Wen-I Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200258865
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 13, 2020
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai, Wen-I Hsu
  • Publication number: 20200212244
    Abstract: A photodetector includes: a substrate; a first semiconductor region, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Application
    Filed: March 13, 2020
    Publication date: July 2, 2020
    Inventors: Chia-Yu WEI, Yu-Ting KAO, Yen-Liang LIN, Wen-I HSU, Hsun-Ying HUANG, Kuo-Cheng LEE, Hsin-Chi CHEN
  • Patent number: 10693039
    Abstract: A light-emitting device comprises a light-emitting stack; a reflective structure comprising a reflective layer on the light-emitting stack and a first insulating layer covering the reflective layer; and a first conductive layer on the reflective structure; wherein the first insulating layer isolates the reflective layer from the first conductive layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 23, 2020
    Assignee: Epistar Corporation
    Inventors: Wen-Luh Liao, Shao-Ping Lu, Hung-Ta Cheng, Shih-I Chen, Chia-Liang Hsu, Shou-Chin Wei, Ching-Pei Lin, Yu-Ren Peng, Chien-Fu Huang, Wei-Yu Chen, Chun-Hsien Chang
  • Patent number: 10629765
    Abstract: A photodetector includes: a substrate having a first doping type; a first semiconductor region having a second doping type, the first semiconductor region extending into the substrate from a front side of the substrate; and a second semiconductor region having the first doping type, the second semiconductor region further extending into the substrate from a bottom boundary of the first semiconductor region, wherein when the photodetector operates under a Geiger mode, the second semiconductor region is fully depleted to absorb a radiation source received from a back side of the substrate.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Yu-Ting Kao, Yen-Liang Lin, Wen-I Hsu, Hsun-Ying Huang, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 10629568
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Patent number: 10608078
    Abstract: A bonded substrate for epitaxial growth and a method for forming the same are disclosed. The method includes steps of providing a first substrate, which has a first dopant concentration; providing a second substrate, which has a second dopant concentration, wherein the second dopant concentration is lower than the first dopant concentration; directly bonding a first surface of the first substrate with a second surface of the second substrate to form a bonded substrate; annealing the bonded substrate to form a high impedance layer in the bonded substrate; and removing part of the second substrate to expose the high impedance layer depending on the requirements whereby, the bonded substrate formed by the method could have a heavily doped substrate which includes a stronger strength and the impedance layer formed thereon, which could effectively increase the substrate strength, reduce the leakage current, and sustains a higher breakdown voltage.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 31, 2020
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Man-Hsuan Lin, Wen-Ching Hsu
  • Publication number: 20200075659
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Publication number: 20200075328
    Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (?) and 500 angstroms.
    Type: Application
    Filed: July 16, 2019
    Publication date: March 5, 2020
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chun-I Fan, Wen-Ching Hsu
  • Patent number: 10553761
    Abstract: A light-emitting device includes a metal connecting structure; a metal reflective layer on the metal connecting structure; a barrier layer between the metal connecting structure and the metal reflective layer; a light-emitting stack on the metal reflective layer; a dielectric layer between the light-emitting stack and the metal reflective layer, and a first extension electrode and a second extension electrode on the light-emitting stack and away from the metal reflective layer. The dielectric layer includes a first part and a second part separated from the first part from a cross section of the light-emitting device. The first extension electrode and the second extension electrode respectively align with the first part and the second part. From a cross section of the light-emitting stack, the first extension electrode has a first width and the first part has a second width larger than the first width.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 4, 2020
    Assignee: Epistar Corporation
    Inventors: Fu Chun Tsai, Wen Luh Liao, Shih I Chen, Chia Liang Hsu, Chih Chiang Lu
  • Patent number: 10535697
    Abstract: An image sensor structure that includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; a second interconnect structure formed on the second semiconductor substrate, wherein the first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates; and a backside deep contact (BDCT) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Feng-Chi Hung, Shuang-Ji Tsai, Jen-Shyan Lin, Shu-Ting Tsai, Wen-I Hsu
  • Patent number: 10475637
    Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: November 12, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Ying-Ru Shih, Wen-Ching Hsu
  • Publication number: 20190304831
    Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.
    Type: Application
    Filed: March 15, 2019
    Publication date: October 3, 2019
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Ying-Ru Shih, Chih-Yuan Chuang, Chi-Tse Lee, Chun-I Fan, Wen-Ching Hsu
  • Patent number: 10388518
    Abstract: An epitaxial substrate and a method of manufacturing the same are provided. The epitaxial substrate includes a handle substrate, a heat dissipation layer on the handle substrate, a high-resistance silicon substrate on the heat dissipation layer, and a III-V semiconductor layer grown on the high-resistance silicon substrate. The heat dissipation layer has high thermal conductivity. The high-resistance silicon substrate has a resistance more than 100 ohm·cm. Diameters of the high-resistance silicon substrate and the III-V semiconductor film are smaller than a diameter of the handle substrate, such that the epitaxial substrate is a convex substrate.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 20, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Chun-I Fan, Chih-Yuan Chuang, Man-Hsuan Lin, Wen-Ching Hsu
  • Publication number: 20190252354
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Publication number: 20190244990
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10367118
    Abstract: A light-emitting diode, comprises an active layer for emitting a light ray; an upper semiconductor stack on the active layer, wherein the upper semiconductor stack comprises a window layer; a reflector; and a lower semiconductor stack between the active layer and the reflector; wherein the thickness of the window layer is small than or equal to 3 ?m, and the thickness of the lower semiconductor stack is small than or equal to 1 ?m.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 30, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Yu-Ren Peng, Tzu-Chieh Hsu, Shih-I Chen, Rong-Ren Lee, Hsin-Chan Chung, Wen-Luh Liao, Yi-Chieh Lin
  • Publication number: 20190172977
    Abstract: A light-emitting device includes a metal connecting structure; a metal reflective layer on the metal connecting structure; a barrier layer between the metal connecting structure and the metal reflective layer; a light-emitting stack on the metal reflective layer; a dielectric layer between the light-emitting stack and the metal reflective layer, and a first extension electrode and a second extension electrode on the light-emitting stack and away from the metal reflective layer. The dielectric layer includes a first part and a second part separated from the first part from a cross section of the light-emitting device. The first extension electrode and the second extension electrode respectively align with the first part and the second part. From a cross section of the light-emitting stack, the first extension electrode has a first width and the first part has a second width larger than the first width.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 6, 2019
    Inventors: Fu Chun TSAI, Wen Luh LIAO, Shih I CHEN, Chia Liang HSU, Chih Chiang LU
  • Patent number: 10276622
    Abstract: An image-sensor device includes a substrate including a pixel region and a logic region. A logic transistor is disposed in the logic region and is surrounded by a logic isolation feature. A radiation-sensing region is disposed in the pixel region of the substrate. An epitaxial pixel isolation feature is disposed in the pixel region and surrounds the radiation-sensing region. A doped region with a same doping polarity as the radiation-sensing region is located between a bottom of the radiation-sensing region and the back surface of the substrate. The epitaxial pixel isolation feature is in direct contact with the doped region. The doped region extends continuously under the pixel region and the logic region. The epitaxial pixel isolation feature is in direct contact with the doped region, and the logic isolation feature is spaced apart from the doped region.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-I Hsu, Feng-Chi Hung, Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 10269768
    Abstract: A method includes bonding a first wafer to a second wafer, with a first plurality of dielectric layers in the first wafer and a second plurality of dielectric layers in the second wafer bonded between a first substrate of the first wafer and a second substrate in the second wafer. A first opening is formed in the first substrate, and the first plurality of dielectric layers and the second wafer are etched through the first opening to form a second opening. A metal pad in the second plurality of dielectric layers is exposed to the second opening. A conductive plug is formed extending into the first and the second openings.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Jeng-Shyan Lin, Wen-I Hsu, Feng-Chi Hung, Dun-Nian Yaung, Ying-Ling Tsai
  • Publication number: 20190115382
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate having a first photodetector region and forming a gate material over the gate dielectric layer. A dielectric protection layer is deposited over the gate dielectric layer and a first sidewall spacer is formed along a side of the gate material. The dielectric protection layer extends from a first location directly over the first photodetector region to a second location between the first sidewall spacer and the gate dielectric layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Chih-Yu Lai, Jiech-Fun Lu, Yeur-Luen Tu