Abstract: A local area network routing switch for routing data transmissions between buses includes a set of input buffers, each for receiving and storing successive data transmissions arriving via a corresponding one of the bus. The switch also includes a set of output buffers for forwarding data transmissions outward via a corresponding bus, and a routing system for selectively routing data transmissions from the input buffers to the output buffers in response to routing requests from the input buffers. The routing system sends STATUS data to each input buffer indicating which output buffers are busy receiving data transmissions and which output buffers are idle. An input buffer makes a routing request only when it stores a data transmission to be forwarded to an idle output port. If its longest-stored data transmission is destined for a busy output port, it may send a routing request for a more recently stored data transmission if that data transmission is to be forwarded to an idle output buffer.

Abstract: A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

Abstract: An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

Abstract: An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller.

Abstract: A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data.

Abstract: A local area network switch includes a set of input ports each receiving and storing incoming packets from a corresponding network station, a set of output ports each forwarding packets to a corresponding network station, and a switching system for routing packets from the input ports to the output ports. The output ports are interconnected to form an output token passing ring and the input ports are interconnected to form an input token passing ring. Whenever an idle output port receives the output token, it holds the output token and signals the input ports to start an input token passing cycle. During an input token passing cycle, an input port storing a packet destined for an output token holder terminates the input token passing cycle when it receives the input token and signals the switching system to establish a connection to the output token holder. To fairly distribute arbitration priority, input and output ports starting positions are rotated for successive input and output token passing cycles.

Abstract: A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.

Abstract: A hierarchical crosspoint array is formed by switch cells occupying separate rectangles in a common plane of an integrated circuit. The switch cells are arranged to form square subarrays which, along with a corresponding set of control cells form a compact square shaped crosspoint array. Each switch cell includes three I/O lines crossing in two orthogonal directions and mating with I/O lines of adjacent switch cells to form two orthogonal arrays of I/O lines. Pairs of orthogonal I/O lines are permanently interconnected where they intersect in switch cells along a main diagonal of the array to provide signal paths leading from separate ports along the edges of the array each extending the length and width of the crosspoint array. Each switch cell of a subarray selectively interconnects two such signal paths to provide a signal path between two ports in response to a combination of states of a bit stored in the switch cell and a bit stored in a control cell corresponding to the subarray.

Abstract: A hierarchical crossbar switch includes several switch arrays, each switch array including several switch cells. Each switch cell interconnects a unique pair of signal ports and provides a bi-directional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array stores input data indicating particular switch cells to be switched on. A second memory array stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch also includes a logic cell array that reads the data stored in the first and second memories and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

Abstract: A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

Abstract: A field programmable logic module provides a set of sockets for mounting electronic components, a set of connector pins for providing external access to the board, and a set of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports can be programmed to provide various types of buffering and logic operations on the signals routed by the FPIDs.

Abstract: A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up.

Abstract: A field programmable circuit board provides a set of sockets for receiving electronic components, a set of connector pins for providing external access to the board and an array of field programmable interconnect devices (FPIDs). The FPIDs are buffered, multiple port cross-point switches that may be programmed by a host computer to selectively connect terminals of the components mounted in the sockets to one another or to the external connector pins. Signal buffers within the FPID ports automatically sense direction of flow of bidirectional signals routed by the FPIDs and buffer the signals in the appropriate direction. Each FPID buffer also samples and stores data indicating states of the buffered signals over several system clock cycles for subsequent read out by the host computer.

Abstract: A field programmable interconnect device (FPID) flexibly interconnects a set of electronic components such as integrated circuits and other devices to one another. The FPID is an integrated circuit chip including a set of ports and a cross-point switch that can be programmed to logically connect any one port to any other port. Each FPID buffer port may be programmed to operate in various modes including unidirectional and bi-directional, with or without tristate control, and to operate at various input or output logic levels with adjustable pull up currents. Each FPID buffer port may also be programmed to perform various operations on buffered signals including adjustably delaying the signal, inverting it or forcing it high or low. The FPID is linked to a host computer via a bus that permits the host computer to program the FPID to make the desired connections, to select various modes of operation of buffers within the FPID and to read out data stored in the FPID.