Abstract: A dynamic random access memory (DRAM) device is provided. The DRAM device includes a circuit substrate, a light emitting element, a first light-permeable thermal dissipation element, and a first light blocking element. At least one DRAM chip is disposed on the circuit substrate. The light emitting element is disposed on the circuit substrate and coupled to the circuit substrate. The first light-permeable thermal dissipation element is disposed on the circuit substrate. The first light blocking element is disposed between the first light-permeable thermal dissipation element and the circuit substrate, and the first light blocking element is disposed on the first light-permeable thermal dissipation element.

Abstract: A motor operating system includes a parameter-setting module and a control circuit. The parameter-setting module generates a first parameter-setting corresponding to a first operating stage through a user interface, and determines whether a first operating status conforms to a first threshold setting. The control circuit is coupled to a motor, receives the first parameter-setting corresponding to the first operating status, drives the motor according to a first driving signal corresponding to the first parameter-setting, and outputs the first operating status corresponding to the first driving signal. When the first operating status does not conform the first threshold setting, the parameter-setting module generates an adjusted first parameter-setting. When the first operating status conforms the first threshold setting, the parameter-setting module sets the first parameter-setting as a first optimal parameter-setting.

Abstract: A short-circuit detection circuit is adapted to a full-bridge driver which includes the first and second high-side transistors respectively coupled from a supply voltage to the first and second output nodes and the first and second low-side transistors respectively coupled from the first and second output nodes to a ground. The short-circuit detection circuit includes the first and second voltage dividers respectively receiving voltages of the first and second output nodes to respectively generate the first and second voltages, the high-side and low-side selectors respectively selecting the first voltage and the second voltage to respectively generate a high-side voltage and a low-side voltage, a high-side comparator generating a high-side short-circuit signal when the high-side voltage is lower than a high-side reference voltage, and a low-side comparator generating a low-side short-circuit signal when the low-side voltage exceeds the low-side reference voltage.

Abstract: A motor operating system includes a parameter-setting module and a control circuit. The parameter-setting module generates a first parameter-setting corresponding to a first operating stage through a user interface, and determines whether a first operating status conforms to a first threshold setting. The control circuit is coupled to a motor, receives the first parameter-setting corresponding to the first operating status, drives the motor according to a first driving signal corresponding to the first parameter-setting, and outputs the first operating status corresponding to the first driving signal. When the first operating status does not conform the first threshold setting, the parameter-setting module generates an adjusted first parameter-setting. When the first operating status conforms the first threshold setting, the parameter-setting module sets the first parameter-setting as a first optimal parameter-setting.

Abstract: A motor operating system includes a parameter-setting module and a control circuit. The parameter-setting module generates a first parameter-setting corresponding to a first operating stage through a user interface, and determines whether a first operating status conforms to a first threshold setting. The control circuit is coupled to a motor, receives the first parameter-setting corresponding to the first operating status, drives the motor according to a first driving signal corresponding to the first parameter-setting, and outputs the first operating status corresponding to the first driving signal. When the first operating status does not conform the first threshold setting, the parameter-setting module generates an adjusted first parameter-setting. When the first operating status conforms the first threshold setting, the parameter-setting module sets the first parameter-setting as a first optimal parameter-setting.

Abstract: A short-circuit detection circuit is adapted to a full-bridge driver which includes the first and second high-side transistors respectively coupled from a supply voltage to the first and second output nodes and the first and second low-side transistors respectively coupled from the first and second output nodes to a ground. The short-circuit detection circuit includes the first and second voltage dividers respectively receiving voltages of the first and second output nodes to respectively generate the first and second voltages, the high-side and low-side selectors respectively selecting the first voltage and the second voltage to respectively generate a high-side voltage and a low-side voltage, a high-side comparator generating a high-side short-circuit signal when the high-side voltage is lower than a high-side reference voltage, and a low-side comparator generating a low-side short-circuit signal when the low-side voltage exceeds the low-side reference voltage.

Abstract: A motor operating system includes a parameter-setting module and a control circuit. The parameter-setting module generates a first parameter-setting corresponding to a first operating stage through a user interface, and determines whether a first operating status conforms to a first threshold setting. The control circuit is coupled to a motor, receives the first parameter-setting corresponding to the first operating status, drives the motor according to a first driving signal corresponding to the first parameter-setting, and outputs the first operating status corresponding to the first driving signal. When the first operating status does not conform the first threshold setting, the parameter-setting module generates an adjusted first parameter-setting. When the first operating status conforms the first threshold setting, the parameter-setting module sets the first parameter-setting as a first optimal parameter-setting.

Abstract: A digital phase-locked loop is provided. The digital phase-locked loop includes: a phase-locked loop, for generating an output frequency according to a reference frequency; and a numerically-controlled oscillator, coupled to the phase-locked loop, for generating the reference frequency, in which the numerically-controlled oscillator includes: a phase accumulator (PA), for outputting a sawtooth signal according to a clock signal and a frequency control word; and a most significant bit (MSB) detector, coupled to the phase accumulator, for detecting a most significant bit of the sawtooth signal outputted from the phase accumulator, thereby generating the reference frequency with a square waveform.

Abstract: A digital phase-locked loop is provided. The digital phase-locked loop includes: a phase-locked loop, for generating an output frequency according to a reference frequency; and a numerically-controlled oscillator, coupled to the phase-locked loop, for generating the reference frequency, in which the numerically-controlled oscillator includes: a phase accumulator (PA), for outputting a sawtooth signal according to a clock signal and a frequency control word; and a most significant bit (MSB) detector, coupled to the phase accumulator, for detecting a most significant bit of the sawtooth signal outputted from the phase accumulator, thereby generating the reference frequency with a square waveform.

Abstract: A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.

Abstract: A one-shot circuit capable of being integrated into a chip generates a frequency-dividing signal according to a reference clock signal of a clock signal generator by means of a frequency-dividing circuit. In this way, the order of the magnitude of the cycle length of the frequency-dividing signal can be raised up by increasing the frequency-dividing times in the frequency-dividing circuit, so that the resistance and the capacitance of an RC oscillator of the clock signal generator are effectively reduced. Therefore, the circuited area occupied by the RC oscillator of the clock signal generator is reduced, so that the one shot circuit can be integrated into a chip without increasing the cost.

Abstract: A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.

Abstract: A packet preamble search method is disclosed for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.

Abstract: The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.

Abstract: The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated signal, an extracting module coupling to the operation module and determining a first and a second threshold value according to the operated signal, a comparing signal coupling to the extracting module and comparing the operated signal with the first and second threshold values to generate a first and a second processing signal, and a latch module latching the first and second processing signals to generate an output signal.

Abstract: A calibration loop includes an oscillator, an integrator, an amplitude comparator, and a working voltage adjuster. The oscillator is used for generating a reference clock signal. The integrator is coupled to the oscillator for generating an output amplitude according to the reference clock signal and a working voltage. The first input end of the amplitude comparator is coupled to the integrator and the second input end of the amplitude comparator is coupled to the oscillator. The amplitude comparator is used for comparing the output amplitude of the integrator with an amplitude of the reference clock signal of the oscillator and outputting a comparison result. The input end of the working voltage adjuster is coupled to the amplitude comparator, and the output end of the working voltage adjuster is coupled to the integrator. The working voltage adjuster is used for tuning the input working voltage according to the comparison result.

Abstract: A Gaussian Frequency Shift Keying/Frequency Shift Keying (GFSK/FSK) modulation circuit implemented in a digital manner comprises a frequency divider for dividing frequency of an inputted clock signal to get a sampling signal, a buffer coupled to the frequency divider for storing inputted data, an integrator coupled to the buffer for processing integration according to the data outputted from the buffer, a first read only memory coupled to the integrator for transferring the data outputted from the integrator according to a cosine function, and a second read only memory coupled to the integrator for transferring the data outputted from the integrator according to a sine function.

Abstract: A packet preamble search method for locating a packet preamble with multiple predetermined patterns of a regular form within a received transmission signal with sequential multiple patterns. The pattern of the received transmission signal and the predetermined pattern of the packet preamble have the same length with even bits. The pattern of the transmission signal is sequentially compared with the predetermined pattern. A hit count is increased and a miss count is reset when the pattern of the transmission signal matches the predetermined pattern. The miss count is increased and the hit count is decreased when the pattern of the transmission signal does not match the predetermined pattern. The hit count and the miss count are reset when the hit count is less than or equal to the miss count. An address matching procedure is activated when the hit count exceeds or is equal to a threshold value.