Abstract: A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Abstract: A self-configuring memory subsystem for a computer system allows the insertion of memory modules into any of the available expansion sockets without the need for setting switches or inserting the modules in a predefined or restricted sequence and without the requirement of additional logic circuitry or microcode in the computer. Each of the memory modules utilized with the subsystem has a number of size identification bits, each bit being connected to a known value, such as ground or left floating. The size bits are detected by logic circuitry embodied in a programmable logic device (PLD) so that the total memory space may be properly mapped. The PLD is programmed so that it uses the identification bits to "map" the installed memory modules into the logical memory address space as accessed by the memory controller so that each memory location of the memory modules has an allocated memory location without addressing ambiguities.