Patents by Inventor Wen-Jen Wang

Wen-Jen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250017121
    Abstract: A resistive memory structure including a substrate, a dielectric layer, a conductive plug, a resistive memory device, a spacer, and a protective layer is provided. The dielectric layer is located on the substrate. The conductive plug is located in the dielectric layer. The conductive plug has a protrusion portion located outside the dielectric layer. The resistive memory device is located on the conductive plug. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The first electrode is located on the conductive plug. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The spacer is located on a sidewall of the resistive memory device. The protective layer is located on a sidewall of the protrusion portion and between the first electrode and the dielectric layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: January 9, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Patent number: 12193345
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: January 7, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240431219
    Abstract: An RRAM includes a bottom electrode, a resistive switching layer, a top electrode and a cap layer stacked from bottom to top. The cap layer includes a top surface. A first spacer contacts a first sidewall of the bottom electrode, and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and contacts a third spacer of the top electrode. A thickness of the first spacer is greater of a thickness of the second spacer. The first spacer and the second spacer do not cover the topmost surface of the cap layer.
    Type: Application
    Filed: July 19, 2023
    Publication date: December 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Publication number: 20240407274
    Abstract: A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; a bottom electrode on the conductive via and the first dielectric layer, a resistive switching layer on the bottom electrode; and a cone-shaped top electrode on the resistive switching layer. The cone-shaped top electrode can produce increased and concentrated electric field during operation, which facilitates the filament forming process.
    Type: Application
    Filed: July 10, 2023
    Publication date: December 5, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Publication number: 20240407273
    Abstract: A resistive memory device includes a first dielectric layer, a via connection structure, and a resistive switching element. The via connection structure is disposed in the first dielectric layer, and the resistive switching element is disposed on the via connection structure and the first dielectric layer. The resistive switching element includes a titanium bottom electrode, a titanium top electrode, and a variable resistance material. The titanium top electrode is disposed above the titanium bottom electrode, and the variable resistance material is sandwiched between the titanium bottom electrode and the titanium top electrode in a vertical direction. The variable resistance material is directly connected with the titanium bottom electrode and the titanium top electrode, and the titanium bottom electrode is directly connected with the via connection structure.
    Type: Application
    Filed: July 6, 2023
    Publication date: December 5, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Hsiang-Hung Peng, Yu-Huan Yeh, Chuan-Fu Wang
  • Patent number: 12127488
    Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 22, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240334850
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240260490
    Abstract: A resistive memory device includes a substrate; a dielectric layer disposed on the substrate; a conductive via disposed in the dielectric layer; and a memory stack structure disposed on the conductive via and the dielectric layer. The memory stack structure includes a bottom electrode layer, a resistive switching layer on the bottom electrode layer, and a top electrode layer on the resistive switching layer. The top electrode layer includes at least two physically separated sub-electrode portions.
    Type: Application
    Filed: February 21, 2023
    Publication date: August 1, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Patent number: 12041863
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: July 16, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240188306
    Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 6, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang, Hsiang-Hung Peng
  • Publication number: 20240107902
    Abstract: A resistive memory device includes a dielectric layer, a via connection structure, a stacked structure, and an insulating structure. The via connection structure is disposed in the dielectric layer. The stacked structure is disposed on the via connection structure and the dielectric layer. The insulating structure penetrates through the stacked structure in a vertical direction and divides the stacked structure into a first memory cell unit and a second memory cell unit. The first memory cell unit includes a first bottom electrode, and the second memory cell unit includes a second bottom electrode separated from the first bottom electrode by the insulating structure. The via connection structure is electrically connected with the first bottom electrode and the second bottom electrode.
    Type: Application
    Filed: October 20, 2022
    Publication date: March 28, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Yu-Huan Yeh, Chuan-Fu Wang
  • Publication number: 20240074335
    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, atop electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming the RRAM device is also provided.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: UNITED MICROELCTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20240074338
    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11871685
    Abstract: A RRAM device includes a bottom electrode, a resistive material layer, a high work function layer, a top electrode, a hard mask and high work function sidewall parts. The bottom electrode, the resistive material layer, the high work function layer, the top electrode and the hard mask are sequentially stacked on a substrate. The high work function sidewall parts cover sidewalls of the top electrode and sidewalls of the hard mask, thereby constituting a RRAM cell. A method of forming said RRAM device is also provided.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: January 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11864473
    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 2, 2024
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20230413698
    Abstract: A resistive random access memory structure includes a first inter-layer dielectric layer; a bottom electrode disposed in the first inter-layer dielectric layer; a capping layer disposed on the bottom electrode and on the first inter-layer dielectric layer; and a through hole disposed in the capping layer. The through hole partially exposes a top surface of the bottom electrode. A variable resistance layer is disposed within the through hole. A top electrode is disposed within the through hole and on the variable resistance layer. A second inter-layer dielectric layer covers the top electrode and the capping layer.
    Type: Application
    Filed: July 29, 2022
    Publication date: December 21, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20230354724
    Abstract: Provided is a resistive memory structure and a manufacturing method thereof. The resistive memory structure includes a substrate, a dielectric layer, a resistive memory device, a hard mask layer, and a spacer. The dielectric layer is located on the substrate. The dielectric layer has an opening. The resistive memory device is located in the opening and has a protrusion outside the opening. The resistive memory device includes a first electrode, a variable resistance layer, and a second electrode. The variable resistance layer is located on the first electrode. The second electrode is located on the variable resistance layer. The hard mask layer covers a top surface of the variable resistance layer. The spacer covers a sidewall of the variable resistance layer in the protrusion.
    Type: Application
    Filed: May 23, 2022
    Publication date: November 2, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11765915
    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11632888
    Abstract: An RRAM structure includes a substrate. The substrate is divided into a memory cell region and a logic device region. A metal plug is disposed within the memory cell region. An RRAM is disposed on and contacts the metal plug. The RRAM includes a top electrode, a variable resistive layer, and a bottom electrode. The variable resistive layer is disposed between the top electrode and the bottom electrode. The variable resistive layer includes a first bottom surface. The bottom electrode includes a first top surface. The first bottom surface and the first top surface are coplanar. The first bottom surface only overlaps and contacts part of the first top surface.
    Type: Grant
    Filed: January 9, 2022
    Date of Patent: April 18, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
  • Publication number: 20230020564
    Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.
    Type: Application
    Filed: August 17, 2021
    Publication date: January 19, 2023
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang