Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract: A method of fabricating a load resistor for an SRAM. A substrate has a polysilicon layer formed thereon through a buried contact process. An inter-layer dielectric layer is formed over the substrate and then patterned to form an opening that exposes the polysilicon layer. A poly via is then formed in the opening to serve as a load resistor. The inter-layer dielectric layer is patterned to form a contact window, which is then filled with a conductive layer to form a contact.

Abstract: A method of manufacturing a borderless contact hole. A substrate having a pad oxide layer and a silicon nitride layer formed thereon is provided. A trench is formed to penetrate through the silicon nitride layer and the pad oxide layer and into the substrate. A first oxide layer is formed in the trench, wherein a surface level of the first oxide layer is lower than that of the substrate. An etching stop layer is formed on the silicon nitride layer, a sidewall of the trench and the first oxide layer, conformally. A second oxide layer is formed on the etching stop layer and fills the trench. A portion of the second oxide layer, a portion of the etching stop layer, the silicon nitride layer and the pad oxide layer are removed. A portion of the second oxide layer in the trench and a portion of the etching stop layer in the trench are removed to form a recess until the surface level constructed by the remaining second oxide layer and the remaining etching stop layer is lower than a surface level of the substrate.