Patents by Inventor Wen-Ju Chen

Wen-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240395907
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Publication number: 20240363436
    Abstract: A method for forming a semiconductor structure is provided.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting KO, Wen-Ju CHEN, Tai-Chun HUANG
  • Patent number: 12087641
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Ko, Wen-Ju Chen, Tai-Chun Huang
  • Patent number: 11855185
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Publication number: 20230395702
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: August 2, 2023
    Publication date: December 7, 2023
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Publication number: 20230335406
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: June 26, 2023
    Publication date: October 19, 2023
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
  • Patent number: 11728173
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
  • Publication number: 20230223304
    Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.
    Type: Application
    Filed: May 11, 2022
    Publication date: July 13, 2023
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Tai-Chun Huang
  • Patent number: 11530479
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Ko, Wen-Ju Chen, Wan-Chen Hsieh, Ming-Fa Wu, Tai-Chun Huang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20220356573
    Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Chung-Ting Ko, Wen-Ju Chen, Wan-Chen Hsieh, Ming-Fa Wu, Tai-Chun Huang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20220344217
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.
    Type: Application
    Filed: April 22, 2021
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting KO, Wen-Ju CHEN, Tai-Chun HUANG
  • Publication number: 20220341724
    Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.
    Type: Application
    Filed: November 8, 2021
    Publication date: October 27, 2022
    Inventors: WEN-JU CHEN, FENG-YU CHANG, YI-TING LIN
  • Publication number: 20220102152
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
  • Publication number: 20220020865
    Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.
    Type: Application
    Filed: March 10, 2021
    Publication date: January 20, 2022
    Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
  • Patent number: 11145746
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co.y, Ltd.
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Publication number: 20210265489
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.
    Type: Application
    Filed: June 19, 2020
    Publication date: August 26, 2021
    Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
  • Patent number: 11064188
    Abstract: A driving method suitable for a head mounted device (HMD) is provided. The driving method includes the following operations: moving a first image capture unit and a second image capture unit of the HMD to respectively capture two left-eye images and two right-eye images; calculating a first eye relief according to at least one left-eye feature in the two left-eye images; calculating a second eye relief according to at least one right-eye feature in the two right-eye images; calculating an interpupillary distance (IPD) according to the first eye relief and the second eye relief; and adjusting, according to the IPD, a distance between a first lens and a second lens of the HMD.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: July 13, 2021
    Assignee: HTC Corporation
    Inventors: Yung-Chen Lin, Wen-Ju Chen, Wei-Chen Chen, Kai-Wen Zheng, Yan-Min Kuo
  • Publication number: 20210037232
    Abstract: A driving method suitable for a head mounted device (HMD) is provided. The driving method includes the following operations: moving a first image capture unit and a second image capture unit of the HMD to respectively capture two left-eye images and two right-eye images; calculating a first eye relief according to at least one left-eye feature in the two left-eye images; calculating a second eye relief according to at least one right-eye feature in the two right-eye images; calculating an interpupillary distance (IPD) according to the first eye relief and the second eye relief; and adjusting, according to the IPD, a distance between a first lens and a second lens of the HMD.
    Type: Application
    Filed: June 29, 2020
    Publication date: February 4, 2021
    Inventors: Yung-Chen LIN, Wen-Ju CHEN, Wei-Chen CHEN, Kai-Wen ZHENG, Yan-Min KUO
  • Patent number: 8274620
    Abstract: An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 25, 2012
    Assignee: Au Optronics Corporation
    Inventors: Chun-Chang Chiu, Jia-Hung Huang, Wen-Ju Chen
  • Publication number: 20120038865
    Abstract: An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode.
    Type: Application
    Filed: October 26, 2011
    Publication date: February 16, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chun-Chang Chiu, Jia-Hung Huang, Wen-Ju Chen