Patents by Inventor Wen-Ju Chen
Wen-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240395907Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Publication number: 20240363436Abstract: A method for forming a semiconductor structure is provided.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting KO, Wen-Ju CHEN, Tai-Chun HUANG
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Patent number: 12087641Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.Type: GrantFiled: April 22, 2021Date of Patent: September 10, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Ko, Wen-Ju Chen, Tai-Chun Huang
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Patent number: 11855185Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: GrantFiled: March 10, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Publication number: 20230395702Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: August 2, 2023Publication date: December 7, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Publication number: 20230335406Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: June 26, 2023Publication date: October 19, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
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Patent number: 11728173Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: GrantFiled: September 30, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
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Publication number: 20230223304Abstract: A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.Type: ApplicationFiled: May 11, 2022Publication date: July 13, 2023Inventors: Wen-Ju Chen, Chung-Ting Ko, Tai-Chun Huang
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Patent number: 11530479Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.Type: GrantFiled: October 18, 2019Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting Ko, Wen-Ju Chen, Wan-Chen Hsieh, Ming-Fa Wu, Tai-Chun Huang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20220356573Abstract: In an embodiment, a method of forming a semiconductor device includes forming a hydrophobic coating on an inner surface of an exhaust line, connecting the exhaust line to a semiconductor processing chamber, introducing a first precursor into the semiconductor processing chamber, introducing a second precursor into the semiconductor processing chamber, wherein the first precursor reacts with the second precursor to form a layer of oxide material, and pumping the first precursor and the second precursor from the semiconductor processing chamber and through the exhaust line.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Chung-Ting Ko, Wen-Ju Chen, Wan-Chen Hsieh, Ming-Fa Wu, Tai-Chun Huang, Yung-Cheng Lu, Chi On Chui
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Publication number: 20220344217Abstract: A method for forming a semiconductor structure is provided. The method includes forming first and second fin structures, wherein each of the first and the second fin structurez include first semiconductor layers and second semiconductor layers alternatingly stacked, and forming a first mask structure to cover the second fin structure. The first mask structure includes a first dielectric layer and a second dielectric layer over the first mask structure, and the first dielectric layer and the second dielectric layer are made of different materials. The method also includes forming a first source/drain feature in the first fin structure, removing the first mask structure, forming a second source/drain feature in the second fin structure, removing the first semiconductor layers of the first fin structure and the second fin structure, thereby forming first nanostructures and second nanostructures, and forming a gate stack around the first and second nanostructures.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Ting KO, Wen-Ju CHEN, Tai-Chun HUANG
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Publication number: 20220341724Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.Type: ApplicationFiled: November 8, 2021Publication date: October 27, 2022Inventors: WEN-JU CHEN, FENG-YU CHANG, YI-TING LIN
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Publication number: 20220102152Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: September 30, 2020Publication date: March 31, 2022Inventors: Wen-Ju Chen, Chung-Ting Ko, Wan-Chen Hsieh, Chun-Ming Lung, Tai-Chun Huang, Chi On Chui
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Publication number: 20220020865Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.Type: ApplicationFiled: March 10, 2021Publication date: January 20, 2022Applicants: Taiwan Semiconductor Manufacturing Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Ju Chen, Chung-Ting Ko, Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui
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Patent number: 11145746Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.Type: GrantFiled: June 19, 2020Date of Patent: October 12, 2021Assignee: Taiwan Semiconductor Manufacturing Co.y, Ltd.Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
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Publication number: 20210265489Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, and forming a sacrificial film over the first semiconductor layer and the second semiconductor layer. The sacrificial film fills an area between the first semiconductor layer and the second semiconductor layer. The method further includes forming a space in the sacrificial film between the first semiconductor layer and the second semiconductor layer and removing the sacrificial film.Type: ApplicationFiled: June 19, 2020Publication date: August 26, 2021Inventors: Wen-Ju Chen, Chung-Ting Ko, Chi On Chui
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Patent number: 11064188Abstract: A driving method suitable for a head mounted device (HMD) is provided. The driving method includes the following operations: moving a first image capture unit and a second image capture unit of the HMD to respectively capture two left-eye images and two right-eye images; calculating a first eye relief according to at least one left-eye feature in the two left-eye images; calculating a second eye relief according to at least one right-eye feature in the two right-eye images; calculating an interpupillary distance (IPD) according to the first eye relief and the second eye relief; and adjusting, according to the IPD, a distance between a first lens and a second lens of the HMD.Type: GrantFiled: June 29, 2020Date of Patent: July 13, 2021Assignee: HTC CorporationInventors: Yung-Chen Lin, Wen-Ju Chen, Wei-Chen Chen, Kai-Wen Zheng, Yan-Min Kuo
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Publication number: 20210037232Abstract: A driving method suitable for a head mounted device (HMD) is provided. The driving method includes the following operations: moving a first image capture unit and a second image capture unit of the HMD to respectively capture two left-eye images and two right-eye images; calculating a first eye relief according to at least one left-eye feature in the two left-eye images; calculating a second eye relief according to at least one right-eye feature in the two right-eye images; calculating an interpupillary distance (IPD) according to the first eye relief and the second eye relief; and adjusting, according to the IPD, a distance between a first lens and a second lens of the HMD.Type: ApplicationFiled: June 29, 2020Publication date: February 4, 2021Inventors: Yung-Chen LIN, Wen-Ju CHEN, Wei-Chen CHEN, Kai-Wen ZHENG, Yan-Min KUO
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Patent number: 8274620Abstract: An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode.Type: GrantFiled: October 26, 2011Date of Patent: September 25, 2012Assignee: Au Optronics CorporationInventors: Chun-Chang Chiu, Jia-Hung Huang, Wen-Ju Chen
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Publication number: 20120038865Abstract: An active device array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units formed between every neighboring two of the scan lines and data lines is provided. Each of the pixel units includes a first active device, a first pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device, a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the first active device, a second active device and a second pixel electrode electrically connected to a corresponding scan line and a corresponding data line through the second active device. The first pixel electrode has a surface area different from that of the second pixel electrode.Type: ApplicationFiled: October 26, 2011Publication date: February 16, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Chun-Chang Chiu, Jia-Hung Huang, Wen-Ju Chen