Abstract: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Abstract: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from and rising above the storage capacitor. Within the memory cell structure, and at a minimum storage capacitor to bitline stud layer separation, a capacitor plate layer is further separated from the bitline stud layer than a capacitor node layer.

Abstract: Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from and rising above the storage capacitor. Within the memory cell structure, and at a minimum storage capacitor to bitline stud layer separation, a capacitor plate layer is further separated from the bitline stud layer than a capacitor node layer.

Abstract: A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer. The substrate at the bottom of the trench is exposed by removing a portion of the linear oxide layer at the bottom of the trench. A polysilicon layer, deposited completely over the mask, fills the trench as well. The polysilicon layer on the mask layer and outside the trench is removed, leaving polysilicon within the trench, which forms a polysilicon plug. A thin conformal barrier layer is formed over the substrate. An insulator layer is deposited above the barrier layer. The isolation layer and barrier layer on top of the mask as well as outside the trench are removed using a chemical mechanical polishing method. The mask is removed.

Abstract: A method for fabricating a conducting structure for a semiconductor device is described. A first dielectric layer is formed on a substrate. The first dielectric layer is etched by using a first photoresist layer, to form original contact holes for exposing surface of the substrate. The first dielectric layer is etched by using a second photoresist layer which is aligned with desired contact holes selected from the original contact holes, to broaden top region of part of the desired contact holes as offset landing regions. A conductive layer is deposited in the desired contact holes, which includes the offset landing region, original contact holes, and on the first dielectric layer. Surface of the conductive layer is planarized to expose the first dielectric layer. In this planarization, original contact structures and desired contact structures having landing plugs are formed, which landing plugs are defined by the first and second photoresist layer.

Abstract: A conducting structure of a COB cell of DRAM includes an piecewise straight active area and substantially straight bitline formed over a semiconductor substrate upon which a first dielectric layer existed. Contact holes are formed over the piecewise straight active area for electrically exposing both nodes (source and drain), of the active area of the access device. An offset landing plug pattern is defined by a photoresist-clear pattern beside, say, the source node of the primary contact pattern and recess-etched into the first dielectric layer and electrically connected to the source node of the primary contact structure finally. The contact structure is then formed by a deposition-etched process, which performs as a landing plug for contact of the upper contact structures. The top area of the landing plug is defined through the additive pattern of the primary contact as well as the offset landing plug pattern.

Abstract: A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor.

Abstract: This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.

Abstract: A method is provided for fabricating totally self-aligned contacts on semiconductor substrates. The method is particularly applicable to dynamic random access memory for reducing the cell area. The method involves patterning the silicon nitride layer for the local oxidation of silicon (LOCOS) process to provide wide device areas for the gate electrode of the FETs, and narrow device areas adjacent and contiguous to the wide device areas on and in which are formed portions of the source/drain areas and the totally self-aligned contacts. The lateral encroachment of the field oxide (bird's beak) into the narrow device areas during the LOCOS process reduce the width of the area to about 0.20 um, and thereby extend the resolution limit of the current lithography (about 0.40 um) used to define the nitride layer.