Abstract: A method of improving yields of dies by adding dummy pattern on open area of multi-project mask is disclosed. Pattern of multi-project mask comprises a main pattern corresponding to a configuration of patterns of different dies and numerous dummy patterns that occupy, even substantially entirely, open area of multi-project mask, where dummy pattern and main pattern are separated by scribing lines. After patterns of multi-project mask are transformed to semiconductor wafer, dies and dummy dies are formed. Obviously, when the semiconductor wafer is treated by some processes such as chemical mechanical polishing and etching, because dies are close to dummy dies then boundaries of dies are protected and then these is no damage on edge of each die.

Abstract: A liquid coating apparatus that is adapted for dispensing two or more different liquids and a method for using such apparatus are disclosed. In the apparatus, when two different liquids are dispensed in the same coating apparatus, two separate drain cups are utilized in which an upper drain cup is constructed in a toroidal shape and formed in two symmetrical halves such that they may be withdrawn from an operating position outwardly to allow a wafer platform and a liquid spray nozzle to be lowered into a lower drain cup for dispensing a second liquid material. The lower drain cup can be mounted concentrically with the upper drain cup. The present invention novel apparatus allows at least two different liquids to be processed in the same coating apparatus such that chemical reactions between the different liquids and the resulting particle formation and contamination problems can be avoided.

Abstract: A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.

Abstract: An apparatus and a method for stepper exposure control by utilizing a shutter assembly formed of electro-optic crystal materials in a photolithographic process are disclosed. In the apparatus, a series of control panels are stacked together to form a shutter assembly. Each of the control panel is formed by depositing a multiplicity of parallel, spaced-apart lines of electro-optic crystal material on a polarizer sheet. Two of such polarizer sheets are then stacked together with the lines parallel to each other and the lines on the top panel overlapping the spacing on the bottom panel. Two bottom panels are formed similarly however, positioned with the lines perpendicular to the lines in the first and second control panel when assembled together in the shutter assembly. A suitable electro-optic crystal material used should withstand a high temperature environment. One of such suitable material is LiNbO3.

Abstract: A structure suitable for aligning two patterned conductive layers that are separated by a dielectric layer is described. Included in the lower pattern is a square and, as part of the upper pattern, four T-shaped capacitor electrodes are provided. The latter are positioned so that, when the alignment is exact, they all overlap the square by the same amount. Thus, under conditions of exact alignment, the capacitance value measured between any one of the top electrodes and the square will be the same for all electrodes. When, however, misalignment occurs, the degree of overlap will change, increasing on one side of the square while decreasing at the opposite side. In this way a comparison of measured capacitance values between electrodes located on opposing sides of the square will indicate whether, and what extent, misalignment has occurred.

Abstract: A method is disclosed for aligning wafers independent of the planarity of layers that are formed on a wafer. In prior art, it is found that when aligning wafers from the front or device side, the alignment of the masks vary because of the variations on the topography of the particular layer in process. Since the topography of a layer is influenced by the cumulative effect of the number of underlying features that are disposed on top of each other, severe misalignments can occur causing defective parts. The problem is eliminated by depositing an infrared reflective (IR) coating over alignment marks formed on oxide layer covering the devices on a wafer, and performing alignment with respect to the reflective marks by projecting IR energy through an IR transparent stage placed under the backside of the wafer and using an IR microscope.

Abstract: A method is disclosed for aligning wafers independent of the processes to which a wafer is subjected. In prior art, it is found that when aligning wafers from the front or device side, the alignment of the masks vary because of the variations on the topography of the particular layer in process. Since the topography of a layer is influenced by the planarization processes used and by the cumulative effect of the number of underlying features that are disposed on top of each other, severe misalignments can occur causing defective parts. The problem is eliminated by forming alignment marks on the backside of the wafer, and performing alignment with respect to the backside marks by projecting IR energy through an IR transparent stage placed under the backside of the wafer and using an IR microscope. An alignment system capable of performing process independent alignment is also disclosed.

Abstract: A thermal processing apparatus for processing a wafer is disclosed. The thermal processing apparatus includes a thermal processing plate, a plurality of spacers, a plurality of locators, and a plurality of sensors. The temperature of the thermal processing plate is controlled within a predetermined range. The spacers are arranged over the thermal processing plate for supporting the wafer, thereby forming a gap between the wafer and the thermal processing plate. The locators, each of which is disposed over one of the spacers, are provided for locating the wafer. The sensors, each of which is disposed over one of the locators, are provided for detecting the position of the wafer.

Abstract: In conjunction with the standard step and repeat process, photocleaving of certain features is achieved by adding to the photoresist mask a photocleaving structure located on the opposite side from the features. The photocleaving structure consists of an opaque area and an attenuating area, separated by a straight line boundary. The attenuating area reduces the amount of actinic radiation that can passes through it by one of several possible elements including alternating opaque and transparent areas that are too small and too closely spaced to be resolved by the radiation. Using an unmodified step and repeat procedure, the latent image of the features that are to be photocleaved is first formed in the usual way (exposure through the mask). When the mask is positioned for the next exposure, the afore-mentioned boundary in the photocleaving structure is arranged to exactly bisect the features so that, after the second exposure, the features will have been photocleaved.

Abstract: A mask is provided, for positive resists, that includes an opaque area and a partially transparent area, there being a straight line boundary between the two. The feature to be photocleaved is a clear area located midway between these areas so that it is bisected by the boundary. For negative resists, the mask includes a clear area and a partially transparent area, the feature to be photocleaved now being an opaque area. The photoresist (positive or negative) is first given a normal dose of actinic radiation, directed through the mask and is developed. After development has been performed, a photocleaved structure results.

Abstract: An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the sake position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.

Abstract: An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the same position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.